 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| REJ09B0355-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2245 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series H8S/2246 H8S/2245 H8S/2244 H8S/2243 H8S/2242 H8S/2241 H8S/2240 HD6432246 HD6472246 HD6432245 HD6432244 HD6432243 HD6432242 HD6432241R HD6412240 Rev.3.00 Revision date: Mar. 26, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.3.00 Mar. 26, 2007 Page ii of xlii REJ09B0355-0300 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.3.00 Mar. 26, 2007 Page iii of xlii REJ09B0355-0300 Rev.3.00 Mar. 26, 2007 Page iv of xlii REJ09B0355-0300 Preface The H8S/2245 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip peripheral functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip peripheral functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), A/D converter, and I/O ports. In addition, an on-chip data transfer controller (DTC) is provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2245 Group enables compact, high-performance systems to be implemented easily. This manual describes the hardware of the H8S/2245 Group. Refer to the H8S/2600 Series and H8S/2000 Series Software Manual for a detailed description of the instruction set. Note: ZTAT is a registered trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page v of xlii REJ09B0355-0300 Rev.3.00 Mar. 26, 2007 Page vi of xlii REJ09B0355-0300 Main Revisions for This Edition Item All Page Revision (See Manual for Details) -- * * 1.1 Overview Table 1.1 Overview 2 Company name and brand names amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Designation for categories amended (Before) H8/2245 Series (After) H8/2245 Group Table 1.1 amended CPU * High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations (20-MHz operation) 1.3.2 Pin Functions in Each Operating Mode 8 to 11 Note *2 added Mode 2* 1 Mode 3* 1 Mode 6* 1 Mode 7* 1 PROM Mode* 2 Table 1.2 Pin Functions 11 in Each Operating Mode 1.3.3 Pin Functions Table 1.3 Pin Functions 13 Notes: 1. Cannot be used in the H8S/2240. 2. NC should be left open. Description amended Operating mode control ... H8S/2245 Group is operating. Except for mode changing, be sure to fix the levels of the mode pins (MD2 to MD0) by pulling them down or pulling them up until the power turns off. 2.1.1 Features 20 Description amended * High-speed operation Maximum clock rate: 20MHz 8/16/32-bit register-register add/subtruct: 50 ns (20-MHz operation) 8 x 8-bit register-register multiply: 600 ns (20-MHz operation) 16 / 8-bit register-register divide: 600 ns (20-MHz operation) 16 x 16-bit register-register multiply: 1000 ns (20-MHz operation) 32 / 16-bit register-register divide: 600 ns (20-MHz operation) Rev.3.00 Mar. 26, 2007 Page vii of xlii REJ09B0355-0300 Item 2.3 Address Space Page Revision (See Manual for Details) 27 Description amended ... address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. 2.6.1 Overview Table 2.1 Instruction Classification 36 Table 2.1 amended LDM* , STM* 5 5 MOVFPE* , MOVTPE* 3 3 TAS* 4 37 Notes 4 and 5 added Notes: 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Table 2.3 Data Transfer 40 Instructions Note *2 added Size* 1 LDM* 2 STM* 2 Notes: 1. Size refers to the operand size. ... 2. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Table 2.4 Arithmetic Operation Instructions 41, 42 42 Note *2 added Size* 1 TAS* 2 Notes: 1. Size refers to the operand size. ... 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Table 2.10 Block Data Transfer Instructions 48 Table 2.10 amended EEPMOV.W ... else next; Transfer a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 66 to Sections 2.10 to 2.10.4 added 2.10.4 Access Methods 70 for Registers with WriteOnly Bits 2.10 Usage Notes to Rev.3.00 Mar. 26, 2007 Page viii of xlii REJ09B0355-0300 Item 3.4 Pin Functions in Each Operating Mode Table 3.3 Pin Functions in Each Operating Mode 5.1.2 Block Diagram Figure 5.1 Block Diagram Page Revision (See Manual for Details) 77 Port E description in mode 4 amended (Before) P* /D (After) P/D* 1 1 104 Figure 5.1 amended (Before) IRQ input (After) IRQ input Figure 5.3 amended (Before) IRQn input pin (After) IRQn input pin Note added Note: n = 7 to 0 Description amended When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. ... Section 5.5.3 added 5.3.1 External Interrupts 112 Figure 5.3 Timing of Setting IRQnF 5.5.1 Contention 126 between Interrupt Generation and Disabling 5.5.3 Times when Interrupts Are Disabled 5.5.5 IRQ Interrupt 5.5.6 NMI Interrupt Usage Notes 6.3.6 Chip Select Signals Figure 6.3 CSn Signal Output Timing (n = 0 to 3) 6.4 Basic Timing to 6.4.3 External Address Space Access Timing 150 to 153 127 127, 128 150 Sections 5.5.5 and 5.5.6 added Figure 6.3 title amended Sections 6.4 to 6.4.3 added Rev.3.00 Mar. 26, 2007 Page ix of xlii REJ09B0355-0300 Item 6.5.5 Wait Control Figure 6.18 Example of Wait State Insertion Timing Page Revision (See Manual for Details) 165 Figure 6.18 amended By program wait T1 T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. 7.2.5 DTC Transfer Count Register A (CRA) 184 Description amended ... In repeat mode or block transfer mode, ... (CRAL). In repeat mode, CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size while CRAL functions as an 8bit block size counter (1 to 256). CRAL is decremented by 1 ... Rev.3.00 Mar. 26, 2007 Page x of xlii REJ09B0355-0300 Item 7.2.8 DTC Vector Register (DTVECR) Page Revision (See Manual for Details) 186 Bit figure amended Bit : 7 6 5 0 4 0 3 0 2 0 1 0 0 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : 0 0 R/(W)*1 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 Notes 1 and 2 amended Notes: 1. A value of 1 can only be written to the SWDTE bit. 2. DTVEC6 to DTVEC0 bits can only be written when SWDTE = 0. Bit 7DTC Software Activation Enable (SWDTE) Description deleted (Before) ... Enables or disables DTC activation by software. The SWDTE bit is cleared by writing 0 after reading 1. (After) Enables or disables DTC activation by software. Condition 2 added [Clearing conditions] 1. When DISEL = 0 and ... 2. When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. 7.3.2 Activation Sources 190 Description added ...The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0. As there are a number of activation sources, the activation source flag is not cleared with the last byte (or word) transfer. Take appropriate measures at each interrupt. 199 Description added ... Figure 7.9 shows the memory map for chain transfer. When activated, the DTC reads the register information start address stored at the vector address, which corresponds to the activation request, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. 7.3.8 Chain Transfer Rev.3.00 Mar. 26, 2007 Page xi of xlii REJ09B0355-0300 Item 8.2.2 Register Configuration Page Revision (See Manual for Details) 214 Port 1 Data Direction Register (P1DDR) Description amended ... an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P1DDR is initialized to H'00 ... 8.3.2 Register Configuration 225 Port 2 Data Direction Register (P2DDR) Description amended ... makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P2DDR is initialized to H'00 ... 8.4.2 Register Configuration 230 Port 3 Data Direction Register (P3DDR) Description amended ... an undefined value will be read. P3DDR cannot be modified. Setting a P3DDR bit to 1 ... makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P3DDR is initialized to H'00 ... 8.5.2 Register Configuration 235 Port 4 Register (PORT4) Description amended PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bits 7 to 4 are reserved; ... 8.6.2 Register Configuration 237 Port 5 Data Direction Register (P5DDR) Description amended ... an undefined value will be read. P5DDR cannot be modified. Setting a P5DDR bit to 1 ... makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P5DDR is initialized to H'0 ... Rev.3.00 Mar. 26, 2007 Page xii of xlii REJ09B0355-0300 Item 8.7.2 Register Configuration Page Revision (See Manual for Details) 241 Port A Data Direction Register (PADDR) Description amended ... an undefined value will be read. PADDR cannot be modified. Setting a PADDR bit to 1 ... makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PADDR is initialized to H'0 ... 8.8.2 Register Configuration 248 Port B Data Direction Register (PBDDR) Description amended ... an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PBDDR is initialized to H'00 ... 8.9.2 Register Configuration 254 Port C Data Direction Register (PCDDR) Description amended ... an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PCDDR is initialized to H'00 ... 8.10.2 Register Configuration 260 Port D Data Direction Register (PDDDR) Description amended ... an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PDDDR is initialized to H'00 ... 8.11.2 Register Configuration 266 Port E Data Direction Register (PEDDR) Description amended ... an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PEDDR is initialized to H'00 ... 8.12.2 Register Configuration 272 Port F Data Direction Register (PFDDR) Description amended ... an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PFDDR is initialized by a power-on reset ... Rev.3.00 Mar. 26, 2007 Page xiii of xlii REJ09B0355-0300 Item 8.13.2 Register Configuration Page Revision (See Manual for Details) 278 Port G Data Direction Register (PGDDR) Description amended ... an undefined value will be read. PGDDR cannot be modified. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PGDDR is initialized by a power-on reset ... 8.14 Handling of Unused Pins 9.2.1 Timer Control Register (TCR) 283 294 Section 8.14 added Bits 4 and 3Clock Edge 1 and 0 (CKEG1, CKEG0) Note amended Note: Internal clock edge selection is valid when the input clock is /4 or slower. If /1 is selected as the input clock, this setting is ignored and count at falling edge of is selected. 9.2.5 Timer Status Register (TSR) 311 Bit 3Input Capture/Output Compare Flag D (TGFD) Description amended [Clearing conditions] * * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0. When 0 is written to TGFD after reading TGFD = 1 Bit 2Input Capture/Output Compare Flag C (TGFC) Description amended [Clearing conditions] * * 312 When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0. When 0 is written to TGFC after reading TGFC = 1 Bit 1Input Capture/Output Compare Flag B (TGFB) Description amended [Clearing conditions] * * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0. When 0 is written to TGFB after reading TGFB = 1 Rev.3.00 Mar. 26, 2007 Page xiv of xlii REJ09B0355-0300 Item 9.2.5 Timer Status Register (TSR) Page Revision (See Manual for Details) 312 Bit 0Input Capture/Output Compare Flag A (TGFA) Description amended [Clearing conditions] * * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0. When 0 is written to TGFA after reading TGFA = 1 9.7 Usage Notes 352 Description added Note that the kinds of operation and contention described below occur during TPU operation. Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 18, Power-Down Modes. Input Clock Restrictions The input clock pulse width must be ... Figure 9.52 Contention between Overflow and Counter Clearing 360 Figure 9.52 amended TGF flag Prohibited TCFV flag Figure 9.53 Contention 361 between TCNT Write and Overflow Figure 9.53 amended TCNT write cycle T1 T2 Address TCNT address Write signal TCNT write data H'FFFF M TCNT TCFV flag Prohibited 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) 367 Description amended ... Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. ... Rev.3.00 Mar. 26, 2007 Page xv of xlii REJ09B0355-0300 Item 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) Page Revision (See Manual for Details) 367 Description amended ... Note, however, that comparison is disabled during the T2 state of a TCORB write cycle. ... Bit 7Compare Match Flag B (CMFB) Description amended [Clearing conditions] * * 371 Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0. 10.2.5 Timer 370 Control/Status Registers 0 and 1(TCSR0, TCSR1) Bit 6Compare Match Flag A (CMFA) Description amended [Clearing conditions] * * Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0. 10.6.1 Setting Module Stop Mode 11.2.2 Timer Control/Status Register (TCSR) 381 Section 10.6.1 added 391 Bit 7Overflow Flag (OVF) Note * added [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF* Note: * When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read at least twice. 11.2.3 Reset Control/Status Register (RSTCSR) 393 Bit 7Watchdog Timer Overflow Flag (WOVF) Description amended [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF 11.4 Interrupts 400 Description added ... whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. 11.5.6 OVF Flag 402 Clearing in Interval Timer Mode Section 11.5.6 added Rev.3.00 Mar. 26, 2007 Page xvi of xlii REJ09B0355-0300 Item 12.2.7 Serial Status Register (SSR) Page Revision (See Manual for Details) 417 Bit 7Transmit Data Register Empty (TDRE) Note * added [Clearing conditions] * * When 0 is written to ... When the DTC* is activated by a TXI interrupt and write data to TDR Note: * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 418 Bit 6Receive Data Register Full (RDRF) Note * added [Clearing conditions] * * When 0 is written to ... When the DTC* is activated by a RXI interrupt and write data to RDR Notes: RDR and the RDRF flag are not affected ... * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 420 Bit 2Transmit End (TEND) Note * added [Clearing conditions] * * When 0 is written to ... When the DTC* is activated by a TXI interrupt and write data to TDR Note: * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page xvii of xlii REJ09B0355-0300 Item Page Revision (See Manual for Details) Table 12.3 amended (MHz) 3.6864 Bit Rate (bit/s) 31250 38400 n -- 0 N -- 2 (MHz) 8 Bit Rate (bit/s) 31250 38400 n 0 -- N 7 -- Error (%) 0.00 -- 12.2.8 Bit Rate Register 422 (BRR) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 4 Error (%) -- 0.00 n 0 -- N 3 -- Error (%) 0.00 -- 423 12.3.2 Operation in Asynchronous Mode Figure 12.4 Sample SCI Initialization Flowchart 437 Note * added to figure 12.4 Set TE and RE* bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Note: * Perform this set operation with the RxD pin in the 1 state. If the RE bit is set to 1 with the RxD pin in the 0 state, it may be misinterpreted as a start bit. Figure 12.5 Sample Serial Transmission Flowchart 438 Note * added to figure 12.5 [3] Serial transmission continuation procedure: ... Checking and clearing of the TDRE flag is automatic when the DTC* is activated by a transmit data empty interrupt (TXI) request, and ... Note: * The case, in which the DTC automatically checks and clears the TDRE flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the TDRE flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Figure 12.7 Sample Serial Reception Data Flowchart 441 Note * added to figure 12.7 [5] Serial reception continuation procedure: ... The RDRE flag is cleared automatically when the DTC* is activated by an RXI interrupt and the RDR value is read. Note: * The case, in which the DTC automatically clears the RDRF flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the RDRF flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Rev.3.00 Mar. 26, 2007 Page xviii of xlii REJ09B0355-0300 Item Page Revision (See Manual for Details) Note * added to figure 12.10 [3] Serial transmission continuation procedure: ... Checking and clearing of the TDRE flag is automatic when the DTC* is activated by a transmit data empty interrupt (TXI) request, and ... Note: * The case, in which the DTC automatically clears the TDRE flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the TDRE flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. 456 Note * added to figure 12.16 [3] Serial transmission continuation procedure: ... Checking and clearing of the TDRE flag is automatic when the DTC* is activated by a transmit data empty interrupt (TXI) request, and ... 447 12.3.3 Multiprocessor Communication Function Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart 12.3.4 Operation in Clocked Synchronous Mode Figure 12.16 Sample Serial Transmission Flowchart Note: * The case, in which the DTC automatically clears the TDRE flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the TDRE flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Figure 12.18 Sample Serial Reception Flowchart 459 Note * added to figure 12.18 [5] Serial reception continuation procedure: ... RDRF flag is cleared automatically when the DTC* is activated by a receive data full interrupt (RXI) request, and ... Note: * The case, in which the DTC automatically clears the RDRF flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the RDRF flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations 461 Note * added to figure 12.20 [5] Serial transmission/reception continuation procedure: ... Also the RDRF flag is cleared automatically when the DTC* is activated by a receive data full interrupt (RXI) request, and ... Notes: When switching from transmit or receive operation to ... * The case, in which the DTC automatically clears the TDRE flag or RDRF flag, occurs only when DISEL in the corresponding DTC transfer is 0 with the transfer counter not being 0. Therefore, the corresponding flag should be cleared by CPU when DISEL in the corresponding DTC transfer is 1, or when DISEL is 0 with the transfer counter being 0. Rev.3.00 Mar. 26, 2007 Page xix of xlii REJ09B0355-0300 Item 12.4 SCI Interrupt Page Revision (See Manual for Details) 462 Note * added When TDRE flag in ... The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC*. The DTC cannot be activated by ... When RDRF flag in ... The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC*. The DTC cannot be activated by an ERI interrupt request. Note: * The flag is not cleared when DISEL is 0 and the transfer counter value is not 0. 12.5 Usage Notes 464 Description added The following points should be noted when using the SCI. Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 18, Power-Down Modes. Relation between Writes to TDR and TDRE Flag 467 Restrictions Concerning DTC Updating ... * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception data full interrupt (RXI). * The flag is cleared only when DISEL in DTC is 0 with the transfer counter not being 0. When DISEL is 1,or DISEL is 0 with the transfer counter being 0, the flag should be cleared by CPU. Note that transmitting, in particular, may not successfully be executed unless the TDRE flag is cleared by CPU. 467 to 472 13.2.2 Serial Status Register (SSR) 479 Description of "Operation in Case of Mode Transition" and "Switching from SCK Pin Function to Port Pin Function" added Bit 2 TEND description amended [Clearing conditions] * * When 0 is written to ... When the DTC* is activated by a TXI interrupt and write data to TDR When TDRE = 1 and ERS = 0 (normal transmission) 12.5 etu after transmission of 1-byte serial character when GM = 0 When TDRE = 1 and ERS = 0 (normal transmission) 11.0 etu after transmission of 1-byte serial character when GM = 1 [Setting conditions] ... * * Rev.3.00 Mar. 26, 2007 Page xx of xlii REJ09B0355-0300 Item 13.2.2 Serial Status Register (SSR) Page Revision (See Manual for Details) 479 Note * added Notes: etu: ... * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 13.3.4 Register Settings 486 SCR Setting Description amended ... When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. ... 13.3.6 Data Transfer Operations 495 Fixing Clock Output Level Description amended When the GM bit in SMR is set to 1, ... In this example, GM is set to 1, ... 496 Data Transfer Operation by DTC Description amended ... If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. When DISEL in DTC is 0 and the transfer counter value is not 0, the TDRE and TEND flags are automatically cleared to 0 when data transfer is performed. If DISEL is 1, or if DISEL is 0 and the transfer counter value is 0, the DTC writes the transfer data to TDR but does not clear the flags. Therefore, the flags should be cleared by the CPU. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DTC is not activated. Thus, the number of bytes specified by the SCI and DTC are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared ... 497 ... If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and transfer of the receive data will be carried out. At this time, the RDRF flag is cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0. If DISEL is 1, or if DISEL is 0 and the transfer counter value is 0, the DTC transfers the receive data but does not clear the flag. Therefore, the flag should be cleared by the CPU. If an error occurs, an error flag is set but the RDRF flag is not. Rev.3.00 Mar. 26, 2007 Page xxi of xlii REJ09B0355-0300 Item 13.4 Usage Notes Page Revision (See Manual for Details) 500 Retransfer Operation Description amended * Retransfer operation when SCI is in receive mode [4] ... If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0. 501 * Retransfer operation when SCI is in transmit mode [9] ... If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0. 14.1.1 Features 503 * High-speed conversion Minimum conversion time: 6.5 s per channel (at 20-MHz operation) Description amended 14.2.2 A/D Control/Status Register (ADCSR) 508 Bit 7A/D End Flag (ADF) Note * added [Clearing conditions] * * When 0 is written to ... When the DTC* is activated by a ADI interrupt and ADDR is read Note: * The flag is cleared only when DISEL in DTC is 0 and the transfer counter value is not 0. 509 Bit 3Clock Select (CKS) Description added ... is stopped (ADST = 0). Set the conversion time to a value equal to or greater than the conversion time indicated in section 19.5, A/D Conversion Characteristics. 14.4.1 Single Mode (SCAN = 0) Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 514 Note * added to figure 14.3 Read conversion result* Rev.3.00 Mar. 26, 2007 Page xxii of xlii REJ09B0355-0300 Item 14.4.3 Input Sampling and A/D Conversion Time Figure 14.5 A/D Conversion Timing Page Revision (See Manual for Details) 517 Figure 14.5 amended (1) Address bus (2) Write signal 14.6 Usage Notes 519 Description added The following points should be noted when using the A/D converter. Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, see section 18, Power-Down Modes. Setting Range of Analog Power Supply and Other Pins 15.2.1 System Control Register (SYSCR) 527 Bit figure amended Bit : 7 -- Initial value : R/W : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 -- 0 RAME 1 R/W 16.1.1 Block Diagram Figure 16.1 Block Diagram of ROM (Example with H8S/2246 and H8S/2245 in Modes 6, 7) 16.2.1 Bus Control Register L (BCRL) 530 Figure 16.1 title amended 531 Bit 5External Address Enable (EAE) Description amended ... or a reserved area* (in the H8S/2244, H8S/2243, ... 16.5.3 Programming Precautions 541 Description amended * The size of the PROM is 128 kbytes. Always set addresses within the range ... Rev.3.00 Mar. 26, 2007 Page xxiii of xlii REJ09B0355-0300 Item 17.7 Note on Crystal Resonator 18.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Table 18.4 Oscillation Stabilization Time Settings Page Revision (See Manual for Details) 553 565 Section 17.7 added Table 18.4 amended STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz 0.41 0.51 0.68 0.82 1.0 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.4 2.7 5.5 1.6 3.3 6.6 2.0 4.1 8.2 1.4 2.7 5.5 2.0 4.1 4.1 8.2 Unit ms 8.2 16.4 10.9 16.4 32.8 10.9 13.1 16.4 21.8 32.8 65.5 13.1 16.4 21.8 26.2 32.8 43.7 65.5 131.1 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 2.7 -- 4.0 -- 8.0 -- s 18.7.1 Hardware Standby Mode 19.5 A/D Conversion Characteristics Table 19.9 A/D Conversion Characteristics A.1 Instruction List Table A.1 Instruction Set 567 Description amended ... Ensure that the RES pin is held low until the clock oscillation stabilizes (as least tOSC1the oscillation stabilization time ... 597 Table 19.9 amended Condition A Item Resolution Conversion time Min 10 13.1 Typ 10 -- Max 10 -- Min 10 9.8 Condition B Typ 10 -- Max 10 -- Min 10 6.5 Condition C Typ 10 -- Max 10 -- Unit bits s 603 (1) Data Transfer Instructions Note * added LDM* STM* Note: * Only register ER0 to ER6 should be used when using the STM/LDM instruction. 607 (2) Arithmetic Instructions Note * added TAS* Note: * Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Table A.4 Number of Cycles in Instruction Execution 633 Notes *3 and *4 added LDM* 3 637 STM* 3 TAS* 4 Notes: 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Mar. 26, 2007 Page xxiv of xlii REJ09B0355-0300 Item Appendix B Register Field Page Revision (See Manual for Details) 659 DTVECR H'FF37 DTC Figure amended Bit : 7 0 R/(W)*1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not ended * When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. DTC software activation is enabled [Holding conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended * During data transfer activated by software 1 Notes: 1. A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. 2. Only write to bits DTVEC6 to DTVEC0 when SWDTE is 0. 662 SCKCR H'FF3A Clock Pulse Generator Figure amended Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 -- 0 R/W 680 SSR0 H'FF7C SCI0 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page xxv of xlii REJ09B0355-0300 Item Appendix B Register Field Page Revision (See Manual for Details) 681 SSR0 H'FF7C Smart Card Interface 0 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 689 SSR1 H'FF84 SCI1 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 690 SSR1 H'FF84 Smart Card Interface 1 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 698 SSR2 H'FF8C SCI2 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 699 SSR2 H'FF8C Smart Card Interface 2 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page xxvi of xlii REJ09B0355-0300 Item Appendix B Register Field Page Revision (See Manual for Details) 702 ADCSR H'FF98 A/D Converter Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 705 TCSR0 H'FFB2 8-Bit Timer Channel 0 TCSR1 H'FFB3 8-Bit Timer Channel 1 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 707 TCSR H'FFBC(W) H'FFBC(R) WDT Note *2 added R/(W)* 1 Overflow Flag [Clearing condition] Cleared by reading TCSR 2 when OVF = 1, then writing 0 to OVF* Notes: The method for writing to ... 1. Can only be written with 0 for flag clearing. 2. When polling OVF with the interval timer interrupt disabled, read TSCR twice or more while OVF is set to 1. 709 RSTCSR H'FFBE(W) H'FFBF(R) WDT Figure amended Watchdog Timer Overflow Flag [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF 716 TSR0 H'FFD5 TPU0 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page xxvii of xlii REJ09B0355-0300 Item Appendix B Register Field Page Revision (See Manual for Details) 722 TSR1 H'FFE5 TPU1 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 728 TSR2 H'FFF5 TPU2 Note *2 added R/(W)* 1 DTC* 2 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Appendix H Package Dimensions Figure H.1 FP-100B Package Dimensions Figure H.2 TFP-100B Package Dimensions 772 Figure H.2 replaced 771 Figure H.1 replaced All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Mar. 26, 2007 Page xxviii of xlii REJ09B0355-0300 Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 1 1 6 7 7 8 12 Section 2 CPU ...................................................................................................................... 19 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU............................................................................. 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space ................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values.......................................................................................... Data Formats ..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function ...................................................... 2.6.4 Basic Instruction Formats .................................................................................... 2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Modes ............................................................................................... 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Reset State............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 19 19 20 21 21 22 27 28 28 29 30 32 33 33 35 36 36 37 39 49 50 50 50 53 57 57 58 59 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Rev.3.00 Mar. 26, 2007 Page xxix of xlii REJ09B0355-0300 2.8.4 Program Execution State...................................................................................... 2.8.5 Bus-Released State............................................................................................... 2.8.6 Power-Down State ............................................................................................... 2.9 Basic Timing..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 External Address Space Access Timing .............................................................. 2.10 Usage Notes ...................................................................................................................... 2.10.1 TAS Instruction.................................................................................................... 2.10.2 STM/LDM Instruction ......................................................................................... 2.10.3 Bit Manipulation Instructions .............................................................................. 2.10.4 Access Methods for Registers with Write-Only Bits ........................................... 61 61 61 62 62 62 64 65 66 66 66 66 68 Section 3 MCU Operating Modes .................................................................................. 71 3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 1 ................................................................................................................. 3.3.2 Mode 2 ................................................................................................................. 3.3.3 Mode 3 ................................................................................................................. 3.3.4 Mode 4 ................................................................................................................. 3.3.5 Mode 5 ................................................................................................................. 3.3.6 Mode 6 ................................................................................................................. 3.3.7 Mode 7 ................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Memory Map in Each Operating Mode ............................................................................ 71 71 72 73 73 73 75 75 75 75 76 76 76 77 77 78 3.2 3.3 3.4 3.5 Section 4 Exception Handling ......................................................................................... 93 4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation ............................................................................ 4.1.3 Exception Sources and Vector Table ................................................................... Reset.................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Types.......................................................................................................... 4.2.3 Reset Sequence .................................................................................................... 93 93 93 94 96 96 96 97 4.2 Rev.3.00 Mar. 26, 2007 Page xxx of xlii REJ09B0355-0300 4.3 4.4 4.5 4.6 4.2.4 Interrupts after Reset............................................................................................ 4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. Interrupts ........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Use of the Stack ................................................................................................. 98 98 99 100 101 102 Section 5 Interrupt Controller .......................................................................................... 103 5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram ..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR).................................................................................... Interrupt Sources ............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table......................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0 ..................................................................................... 5.4.3 Interrupt Control Mode 1 ..................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts ...................................................................... 5.5.3 Times when Interrupts Are Disabled ................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 5.5.5 IRQ Interrupt........................................................................................................ 5.5.6 NMI Interrupt Usage Notes.................................................................................. DTC Activation by Interrupt............................................................................................. 5.6.1 Overview.............................................................................................................. 5.6.2 Block Diagram ..................................................................................................... 5.6.3 Operation ............................................................................................................. 103 103 104 105 105 106 106 107 108 108 109 111 111 112 112 116 116 119 121 124 125 126 126 127 127 127 127 128 128 128 129 129 5.2 5.3 5.4 5.5 5.6 Rev.3.00 Mar. 26, 2007 Page xxxi of xlii REJ09B0355-0300 Section 6 Bus Controller ................................................................................................... 131 6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Bus Width Control Register (ABWCR)............................................................... 6.2.2 Access State Control Register (ASTCR) ............................................................. 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 6.2.4 Bus Control Register H (BCRH) ......................................................................... 6.2.5 Bus Control Register L (BCRL) .......................................................................... Overview of Bus Control .................................................................................................. 6.3.1 Area Partitioning.................................................................................................. 6.3.2 Bus Specifications................................................................................................ 6.3.3 Memory Interfaces............................................................................................... 6.3.4 Advanced Mode................................................................................................... 6.3.5 Areas in Normal Mode ........................................................................................ 6.3.6 Chip Select Signals .............................................................................................. Basic Timing..................................................................................................................... 6.4.1 On-Chip Memory (ROM, RAM) Access Timing ................................................ 6.4.2 On-Chip Peripheral Module Access Timing........................................................ 6.4.3 External Address Space Access Timing .............................................................. Basic Bus Interface ........................................................................................................... 6.5.1 Overview.............................................................................................................. 6.5.2 Data Size and Data Alignment............................................................................. 6.5.3 Valid Strobes........................................................................................................ 6.5.4 Basic Timing........................................................................................................ 6.5.5 Wait Control ........................................................................................................ Burst ROM Interface......................................................................................................... 6.6.1 Overview.............................................................................................................. 6.6.2 Basic Timing........................................................................................................ 6.6.3 Wait Control ........................................................................................................ Idle Cycle.......................................................................................................................... 6.7.1 Operation ............................................................................................................. 6.7.2 Pin States in Idle Cycle ........................................................................................ Bus Release....................................................................................................................... 6.8.1 Overview.............................................................................................................. 6.8.2 Operation ............................................................................................................. 6.8.3 Pin States in External Bus Released State............................................................ 6.8.4 Transition Timing ................................................................................................ 131 131 132 133 134 135 135 136 137 141 143 145 145 146 147 148 149 150 150 151 152 153 153 153 153 155 156 164 166 166 166 168 169 169 172 172 172 172 173 174 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Rev.3.00 Mar. 26, 2007 Page xxxii of xlii REJ09B0355-0300 6.9 6.8.5 Usage Note........................................................................................................... Bus Arbitration.................................................................................................................. 6.9.1 Overview.............................................................................................................. 6.9.2 Operation ............................................................................................................. 6.9.3 Bus Transfer Timing ............................................................................................ 6.9.4 External Bus Release Usage Note........................................................................ 6.10 Resets and the Bus Controller ........................................................................................... 175 175 175 175 176 176 176 Section 7 Data Transfer Controller................................................................................. 177 7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 7.2.1 DTC Mode Register A (MRA) ............................................................................ 7.2.2 DTC Mode Register B (MRB)............................................................................. 7.2.3 DTC Source Address Register (SAR).................................................................. 7.2.4 DTC Destination Address Register (DAR) .......................................................... 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR) ........................................................................ 7.2.9 Module Stop Control Register (MSTPCR) .......................................................... Operation........................................................................................................................... 7.3.1 Overview.............................................................................................................. 7.3.2 Activation Sources ............................................................................................... 7.3.3 DTC Vector Table................................................................................................ 7.3.4 Location of Register Information in Address Space ............................................ 7.3.5 Normal Mode....................................................................................................... 7.3.6 Repeat Mode ........................................................................................................ 7.3.7 Block Transfer Mode ........................................................................................... 7.3.8 Chain Transfer ..................................................................................................... 7.3.9 Operation Timing................................................................................................. 7.3.10 Number of DTC Execution States........................................................................ 7.3.11 Procedures for Using DTC................................................................................... 7.3.12 Examples of Use of the DTC ............................................................................... Interrupts ........................................................................................................................... Usage Notes ...................................................................................................................... 177 177 178 179 180 180 182 183 183 184 184 185 186 187 187 187 189 191 194 195 196 197 199 200 201 203 204 206 206 7.2 7.3 7.4 7.5 Section 8 I/O Ports .............................................................................................................. 207 8.1 Overview........................................................................................................................... 207 Rev.3.00 Mar. 26, 2007 Page xxxiii of xlii REJ09B0355-0300 8.2 Port 1................................................................................................................................. 8.2.1 Overview.............................................................................................................. 8.2.2 Register Configuration......................................................................................... 8.2.3 Pin Functions ....................................................................................................... 8.3 Port 2................................................................................................................................. 8.3.1 Overview.............................................................................................................. 8.3.2 Register Configuration......................................................................................... 8.3.3 Pin Functions ....................................................................................................... 8.4 Port 3................................................................................................................................. 8.4.1 Overview.............................................................................................................. 8.4.2 Register Configuration......................................................................................... 8.4.3 Pin Functions ....................................................................................................... 8.5 Port 4................................................................................................................................. 8.5.1 Overview.............................................................................................................. 8.5.2 Register Configuration......................................................................................... 8.5.3 Pin Functions ....................................................................................................... 8.6 Port 5................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.2 Register Configuration......................................................................................... 8.6.3 Pin Functions ....................................................................................................... 8.7 Port A................................................................................................................................ 8.7.1 Overview.............................................................................................................. 8.7.2 Register Configuration......................................................................................... 8.7.3 Pin Functions ....................................................................................................... 8.7.4 MOS Input Pull-Up Function............................................................................... 8.8 Port B ................................................................................................................................ 8.8.1 Overview.............................................................................................................. 8.8.2 Register Configuration......................................................................................... 8.8.3 Pin Functions ....................................................................................................... 8.8.4 MOS Input Pull-Up Function............................................................................... 8.9 Port C ................................................................................................................................ 8.9.1 Overview.............................................................................................................. 8.9.2 Register Configuration......................................................................................... 8.9.3 Pin Functions ....................................................................................................... 8.9.4 MOS Input Pull-Up Function............................................................................... 8.10 Port D................................................................................................................................ 8.10.1 Overview.............................................................................................................. 8.10.2 Register Configuration......................................................................................... 8.10.3 Pin Functions ....................................................................................................... 8.10.4 MOS Input Pull-Up Function............................................................................... 8.11 Port E ................................................................................................................................ 213 213 214 216 224 224 224 227 229 229 229 232 234 234 234 235 236 236 236 239 240 240 240 244 246 247 247 248 250 252 253 253 254 256 258 259 259 260 262 264 265 Rev.3.00 Mar. 26, 2007 Page xxxiv of xlii REJ09B0355-0300 8.11.1 Overview.............................................................................................................. 8.11.2 Register Configuration......................................................................................... 8.11.3 Pin Functions ....................................................................................................... 8.11.4 MOS Input Pull-Up Function............................................................................... 8.12 Port F................................................................................................................................. 8.12.1 Overview.............................................................................................................. 8.12.2 Register Configuration......................................................................................... 8.12.3 Pin Functions ....................................................................................................... 8.13 Port G ................................................................................................................................ 8.13.1 Overview.............................................................................................................. 8.13.2 Register Configuration......................................................................................... 8.13.3 Pin Functions ....................................................................................................... 8.14 Handling of Unused Pins .................................................................................................. 265 266 268 270 271 271 272 274 277 277 278 281 283 Section 9 16-Bit Timer Pulse Unit (TPU) .................................................................... 285 9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagram ..................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 9.2.1 Timer Control Register (TCR) ............................................................................. 9.2.2 Timer Mode Register (TMDR) ............................................................................ 9.2.3 Timer I/O Control Register (TIOR) ..................................................................... 9.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 9.2.5 Timer Status Register (TSR)................................................................................ 9.2.6 Timer Counter (TCNT)........................................................................................ 9.2.7 Timer General Register (TGR) ............................................................................ 9.2.8 Timer Start Register (TSTR)................................................................................ 9.2.9 Timer Synchro Register (TSYR) ......................................................................... 9.2.10 Module Stop Control Register (MSTPCR) .......................................................... Interface to Bus Master ..................................................................................................... 9.3.1 16-Bit Registers ................................................................................................... 9.3.2 8-Bit Registers ..................................................................................................... Operation........................................................................................................................... 9.4.1 Overview.............................................................................................................. 9.4.2 Basic Functions.................................................................................................... 9.4.3 Synchronous Operation........................................................................................ 9.4.4 Buffer Operation .................................................................................................. 9.4.5 PWM Modes ........................................................................................................ 9.4.6 Phase Counting Mode .......................................................................................... 285 285 289 290 291 292 292 296 298 307 309 313 313 314 315 316 317 317 317 319 319 320 325 328 331 336 9.2 9.3 9.4 Rev.3.00 Mar. 26, 2007 Page xxxv of xlii REJ09B0355-0300 9.5 9.6 9.7 Interrupts........................................................................................................................... 9.5.1 Interrupt Sources and Priorities............................................................................ 9.5.2 DTC Activation.................................................................................................... 9.5.3 A/D Converter Activation.................................................................................... Operation Timing.............................................................................................................. 9.6.1 Input/Output Timing ............................................................................................ 9.6.2 Interrupt Signal Timing ....................................................................................... Usage Notes ...................................................................................................................... 341 341 342 342 343 343 348 352 Section 10 8-Bit Timers..................................................................................................... 363 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 10.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 10.2.6 Module Stop Control Register (MSTPCR) .......................................................... 10.3 Operation .......................................................................................................................... 10.3.1 TCNT Incrementation Timing ............................................................................. 10.3.2 Compare Match Timing....................................................................................... 10.3.3 Timing of External RESET on TCNT ................................................................. 10.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 10.3.5 Operation with Cascaded Connection.................................................................. 10.4 Interrupt Sources............................................................................................................... 10.4.1 Interrupt Sources and DTC Activation ................................................................ 10.4.2 A/D Converter Activation.................................................................................... 10.5 Sample Application........................................................................................................... 10.6 Usage Notes ...................................................................................................................... 10.6.1 Setting Module Stop Mode .................................................................................. 10.6.2 Contention between TCNT Write and Clear........................................................ 10.6.3 Contention between TCNT Write and Increment ................................................ 10.6.4 Contention between TCOR Write and Compare Match ...................................... 10.6.5 Contention between Compare Matches A and B ................................................. 10.6.6 Switching of Internal Clocks and TCNT Operation............................................. 10.6.7 Interrupts and Module Stop Mode ....................................................................... 363 363 364 365 365 366 366 367 367 368 370 373 374 374 375 377 377 378 379 379 379 380 381 381 381 382 383 384 384 386 Rev.3.00 Mar. 26, 2007 Page xxxvi of xlii REJ09B0355-0300 Section 11 Watchdog Timer............................................................................................. 387 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Timer Counter (TCNT)........................................................................................ 11.2.2 Timer Control/Status Register (TCSR) ................................................................ 11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 11.2.4 Notes on Register Access..................................................................................... 11.3 Operation........................................................................................................................... 11.3.1 Watchdog Timer Operation ................................................................................. 11.3.2 Interval Timer Operation ..................................................................................... 11.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 11.4 Interrupts ........................................................................................................................... 11.5 Usage Notes ...................................................................................................................... 11.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 11.5.2 Changing Value of CKS2 to CKS0...................................................................... 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 11.5.4 System Reset by WDTOVF Signal...................................................................... 11.5.5 Internal Reset in Watchdog Timer Mode............................................................. 11.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 387 387 388 389 389 390 390 390 392 394 396 396 398 399 400 400 401 401 401 402 402 402 402 403 403 403 405 406 407 408 408 408 409 409 410 413 417 421 430 Section 12 Serial Communication Interface (SCI) .................................................... 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Receive Shift Register (RSR)............................................................................... 12.2.2 Receive Data Register (RDR) .............................................................................. 12.2.3 Transmit Shift Register (TSR) ............................................................................. 12.2.4 Transmit Data Register (TDR)............................................................................. 12.2.5 Serial Mode Register (SMR)................................................................................ 12.2.6 Serial Control Register (SCR).............................................................................. 12.2.7 Serial Status Register (SSR)................................................................................. 12.2.8 Bit Rate Register (BRR) ...................................................................................... 12.2.9 Smart Card Mode Register (SCMR) .................................................................... Rev.3.00 Mar. 26, 2007 Page xxxvii of xlii REJ09B0355-0300 12.2.10 Module Stop Control Register (MSTPCR) .......................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Overview.............................................................................................................. 12.3.2 Operation in Asynchronous Mode ....................................................................... 12.3.3 Multiprocessor Communication Function ........................................................... 12.3.4 Operation in Clocked Synchronous Mode ........................................................... 12.4 SCI Interrupts.................................................................................................................... 12.5 Usage Notes ...................................................................................................................... 431 432 432 434 445 453 462 464 Section 13 Smart Card Interface ..................................................................................... 473 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Smart Card Mode Register (SCMR) .................................................................... 13.2.2 Serial Status Register (SSR) ................................................................................ 13.2.3 Serial Mode Register (SMR)................................................................................ 13.2.4 Serial Control Register (SCR).............................................................................. 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Pin Connections ................................................................................................... 13.3.3 Data Format ......................................................................................................... 13.3.4 Register Settings .................................................................................................. 13.3.5 Clock.................................................................................................................... 13.3.6 Data Transfer Operations..................................................................................... 13.3.7 Operation in GSM Mode ..................................................................................... 13.4 Usage Notes ...................................................................................................................... 473 473 474 475 475 477 477 478 480 481 482 482 483 484 485 488 490 497 498 Section 14 A/D Converter................................................................................................. 503 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 14.2.3 A/D Control Register (ADCR) ............................................................................ 14.2.4 Module Stop Control Register (MSTPCR) .......................................................... Rev.3.00 Mar. 26, 2007 Page xxxviii of xlii REJ09B0355-0300 503 503 504 505 506 507 507 508 510 511 14.3 Interface to Bus Master ..................................................................................................... 14.4 Operation........................................................................................................................... 14.4.1 Single Mode (SCAN = 0) .................................................................................... 14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 14.4.3 Input Sampling and A/D Conversion Time ......................................................... 14.4.4 External Trigger Input Timing ............................................................................. 14.5 Interrupts ........................................................................................................................... 14.6 Usage Notes ...................................................................................................................... 512 513 513 515 517 518 519 519 Section 15 RAM .................................................................................................................. 525 15.1 Overview........................................................................................................................... 15.1.1 Block Diagram ..................................................................................................... 15.1.2 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 System Control Register (SYSCR) ...................................................................... 15.3 Operation........................................................................................................................... 525 526 526 527 527 527 Section 16 ROM .................................................................................................................. 529 16.1 Overview........................................................................................................................... 16.1.1 Block Diagram ..................................................................................................... 16.1.2 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 Bus Control Register L (BCRL) .......................................................................... 16.3 Operation........................................................................................................................... 16.4 PROM Mode ..................................................................................................................... 16.4.1 PROM Mode Setting............................................................................................ 16.4.2 Socket Adapter and Memory Map ....................................................................... 16.5 Programming..................................................................................................................... 16.5.1 Overview.............................................................................................................. 16.5.2 Programming and Verification............................................................................. 16.5.3 Programming Precautions .................................................................................... 16.5.4 Reliability of Programmed Data .......................................................................... 529 530 530 531 531 532 533 533 533 536 536 536 541 542 Section 17 Clock Pulse Generator .................................................................................. 543 17.1 Overview........................................................................................................................... 17.1.1 Block Diagram ..................................................................................................... 17.1.2 Register Configuration......................................................................................... 17.2 Register Descriptions ........................................................................................................ 17.2.1 System Clock Control Register (SCKCR) ........................................................... 17.2.2 Low Power Control Register (LPWCR) .............................................................. 17.3 Oscillator........................................................................................................................... 543 543 544 544 544 545 546 Rev.3.00 Mar. 26, 2007 Page xxxix of xlii REJ09B0355-0300 17.4 17.5 17.6 17.7 17.3.1 Connecting a Crystal Resonator........................................................................... 17.3.2 External Clock Input............................................................................................ Duty Adjustment Circuit................................................................................................... Medium-Speed Clock Divider .......................................................................................... Bus Master Clock Selection Circuit.................................................................................. Note on Crystal Resonator ................................................................................................ 546 548 553 553 553 553 Section 18 Power-Down Modes...................................................................................... 555 18.1 Overview........................................................................................................................... 18.1.1 Register Configuration......................................................................................... 18.2 Register Descriptions ........................................................................................................ 18.2.1 Standby Control Register (SBYCR) .................................................................... 18.2.2 System Clock Control Register (SCKCR) ........................................................... 18.2.3 Module Stop Control Register (MSTPCR) .......................................................... 18.3 Medium-Speed Mode........................................................................................................ 18.4 Sleep Mode ....................................................................................................................... 18.5 Module Stop Mode ........................................................................................................... 18.5.1 Module Stop Mode .............................................................................................. 18.5.2 Usage Notes ......................................................................................................... 18.6 Software Standby Mode.................................................................................................... 18.6.1 Software Standby Mode....................................................................................... 18.6.2 Clearing Software Standby Mode ........................................................................ 18.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 18.6.4 Software Standby Mode Application Example.................................................... 18.6.5 Usage Notes ......................................................................................................... 18.7 Hardware Standby Mode .................................................................................................. 18.7.1 Hardware Standby Mode ..................................................................................... 18.7.2 Hardware Standby Mode Timing......................................................................... 18.8 Clock Output Disabling Function .................................................................................. 555 556 557 557 558 559 560 561 562 562 563 564 564 564 565 565 566 567 567 567 568 Section 19 Electrical Characteristics.............................................................................. 569 19.1 19.2 19.3 19.4 Absolute Maximum Ratings ............................................................................................. Power Supply Voltage and Operating Frequency Ranges ................................................ DC Characteristics ............................................................................................................ AC Characteristics ............................................................................................................ 19.4.1 Clock Timing ....................................................................................................... 19.4.2 Control Signal Timing ......................................................................................... 19.4.3 Bus Timing .......................................................................................................... 19.4.4 Timing of On-Chip Supporting Modules............................................................. 19.5 A/D Conversion Characteristics........................................................................................ 19.6 Usage Notes ...................................................................................................................... 569 570 572 579 580 582 584 592 597 598 Rev.3.00 Mar. 26, 2007 Page xl of xlii REJ09B0355-0300 Appendix A Instruction Set .............................................................................................. 599 A.1 A.2 A.3 Instruction List .................................................................................................................. 599 Operation Code Map......................................................................................................... 623 Number of States Required for Instruction Execution ...................................................... 627 Appendix B Register Field................................................................................................ 638 B.1 B.2 Register Addresses ............................................................................................................ 638 Register Descriptions ........................................................................................................ 644 Appendix C I/O Port Block Diagrams........................................................................... 730 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Port 1 Block Diagram ....................................................................................................... Port 2 Block Diagram ....................................................................................................... Port 3 Block Diagram ....................................................................................................... Port 4 Block Diagram ....................................................................................................... Port 5 Block Diagram ....................................................................................................... Port A Block Diagram....................................................................................................... Port B Block Diagram....................................................................................................... Port C Block Diagram....................................................................................................... Port D Block Diagram....................................................................................................... Port E Block Diagram ....................................................................................................... Port F Block Diagram ....................................................................................................... Port G Block Diagram....................................................................................................... 730 734 738 741 742 746 747 748 749 750 751 759 Appendix D Pin States ....................................................................................................... 763 D.1 Port States in Each Mode .................................................................................................. 763 Appendix E Pin States at Power-On .............................................................................. 767 E.1 E.2 When Pins Settle from an Indeterminate State at Power-On ............................................ 767 When Pins Settle from the High-Impedance State at Power-On....................................... 768 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode............................................................................................... 769 Appendix G Product Code Lineup.................................................................................. 770 Appendix H Package Dimensions................................................................................... 771 Rev.3.00 Mar. 26, 2007 Page xli of xlii REJ09B0355-0300 Rev.3.00 Mar. 26, 2007 Page xlii of xlii REJ09B0355-0300 Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2245 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, and I/O ports. The on-chip ROM is either PROM (ZTAT) or mask ROM, with a capacity of 128 kbytes, 64 kbytes, or 32 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Seven operating modes, modes 1 to 7, are provided, and there is a choice of address space and single-chip mode or external expansion mode. The features of the H8S/2245 Group are shown in table 1.1. Note: ZTAT is a registered trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page 1 of 772 REJ09B0355-0300 Section 1 Overview Table 1.1 Item CPU Overview Specification * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations (20-MHz operation) 8/16/32-bit register-register add/subtract: 50 ns 16 x 16-bit register-register multiply: 1000 ns 32 / 16-bit register-register divide: 1000 ns * Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit move/arithmetic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions * Two CPU operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space Bus controller * * * * * * * Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area (CS0 to CS3) 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC Data transfer controller (DTC) * * * * Rev.3.00 Mar. 26, 2007 Page 2 of 772 REJ09B0355-0300 Section 1 Overview Item 16-bit timer-pulse unit (TPU) Specification * * * 8-bit timer 2 channels * * * Watchdog timer Serial communication interface (SCI) 3 channels A/D converter * * * * * * * * * I/O ports Memory * * * 3-channel 16-bit timer on-chip Pulse I/O processing capability for up to 8 pins' Automatic 2-phase encoder count capability 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 4 channels Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger 75 I/O pins, 4 input-only pins PROM or mask ROM High-speed static RAM ROM 128 kbytes 128 kbytes 64 kbytes 64 kbytes 32 kbytes 32 kbytes -- RAM 8 kbytes 4 kbytes 8 kbytes 4 kbytes 8 kbytes 4 kbytes 4 kbytes Product Name H8S/2246 H8S/2245 H8S/2244 H8S/2243 H8S/2242 H8S/2241 H8S/2240 Interrupt controller * * * Nine external interrupt pins (NMI, IRQ0 to IRQ7) 34 internal interrupt sources Three priority levels settable Rev.3.00 Mar. 26, 2007 Page 3 of 772 REJ09B0355-0300 Section 1 Overview Item Power-down state Specification * * * * * Operating modes Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Seven MCU operating modes CPU Operating Mode Mode 1 2* 3* 4 5 6* 7* Advanced Normal External Data Bus Description On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode On-Chip ROM Disabled Enabled Enabled Disabled Disabled Enabled Enabled Initial Value 8 bits 8 bits -- 16 bits 8 bits 8 bits -- Maximum Value 16 bits 16 bits -- 16 bits 16 bits 16 bits -- Note: * Cannot be used in the H8S/2240. Clock pulse generator Packages * * * Built-in duty correction circuit 100-pin plastic QFP (FP-100B) 100-pin plastic TQFP (TFP-100B) Rev.3.00 Mar. 26, 2007 Page 4 of 772 REJ09B0355-0300 Section 1 Overview Item Product lineup Mask ROM Version HD6432246 HD6432245 HD6432244 HD6432243 HD6432242 HD6432241R HD6432240 Specification Model ZTAT Version HD6472246 -- -- -- -- -- -- ROM/RAM (Bytes) 128 k/8 k 128 k/4 k 64 k/8 k 64 k/4 k 32 k/8 k 32 k/4 k --/4 k Packages FP-100B TFP-100B Rev.3.00 Mar. 26, 2007 Page 5 of 772 REJ09B0355-0300 Section 1 Overview 1.2 Internal Block Diagram Figure 1.1 shows an internal block diagram. PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 Port D PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 Port E VCC VCC VCC VSS VSS VSS VSS VSS VSS Interanal address bus H8S/2000 CPU Internal data bus Interrupt controller DTC Bus conbtroller Peripheral address bus Peripheral data bus Port B MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI PA3 /A19 PA2 /A18 PA1 /A17 PA0 /A16 PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Clock pulse generator WDT PF7 / PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR/IRQ3 PF2 / WAIT / BREQO/IRQ2 PF1 / BACK/IRQ1 PF0 / BREQ/IRQ0 PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3/IRQ7 PG0 / ADTRG/ IRQ6 RAM 8-bit timer P35 / SCK1/IRQ5 P34 / SCK0/IRQ4 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 Port F SCI TPU A/D converter Port 3 Port C ROM* Port A P50 / TxD2 P51 / RxD2 P52 / SCK2 P53 Port G Port 1 Port 2 Port 4 P20 P21 P22 /TMRI0 P23 /TMCI0 P24 /TMRI1 P25 /TMCI1 P26 /TMO0 P27 /TMO1 Note: * There is no ROM in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 6 of 772 REJ09B0355-0300 P10 /TIOCA0/A20 P11 /TIOCB0/A21 P12 /TIOCC0/ TCLKA/A22 P13 /TIOCD0/ TCLKB/A23 P14 /TIOCA1 P15 /TIOCB1/ TCLKC P16 /TIOCA2 P17 /TIOCB2/ TCLKD Figure 1.1 Block Diagram P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Vref AVCC AVSS Port 5 Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement Figure 1.2 shows the pin arrangement of the H8S/2245 Group. PF2/WAIT/BREQO/IRQ2 PF1/BACK/IRQ1 PF3/LWR/IRQ3 P52/SCK2 PF4/HWR P51/RxD2 WDTOVF P50/TxD2 PA3/A19 53 PA2/A18 52 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PF0/IRQ0/BREQ AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 P22/TMRI0 P23/TMCI0 P24/TMRI1 P25/TMCI1 P26/TMO0 P27/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC P10/TIOCA0/A20 P11/TIOCB0/A21 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PA1/A17 PF5/RD PF6/AS EXTAL STBY PF7/ XTAL RES MD2 MD1 MD0 VCC NMI VSS P53 PA0/A16 VSS PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 VCC PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 VSS PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PD0/D8 24 PD1/D9 VSS PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 PE7/D7 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P15/TIOCB1/TCLKC Figure 1.2 H8S/2245 Group Pin Arrangement (FP-100B, TFB-100B: Top View) P17/TIOCB2/TCLKD P35/SCK1/IRQ5 P30/TxD0 P14/TIOCA1 P16/TIOCA2 P31/TxD1 Rev.3.00 Mar. 26, 2007 Page 7 of 772 REJ09B0355-0300 PD2/D10 25 1 2 3 4 5 6 7 8 9 Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions in each of the operating modes. Table 1.2 Pin No. FP-100B, TFP-100B Mode 1 1 P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB Mode 2* P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB 1 Pin Functions in Each Operating Mode Pin Name Mode 3* P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB 1 Mode 4 P12/ TIOCC0/ TCLKA/A22 P13/ TIOCD0/ TCLKB/A23 Mode 5 P12/ TIOCC0/ TCLKA/A22 P13/ TIOCD0/ TCLKB/A23 Mode 6* 1 Mode 7* P12/ TIOCC0/ TCLKA P13/ TIOCD0/ TCLKB 1 PROM 2 Mode* NC P12/ TIOCC0/ TCLKA/A22 P13/ TIOCD0/ TCLKB/A23 2 NC 3 4 P14/TIOCA1 P14/TIOCA1 P14/TIOCA1 P14/TIOCA1 P14/TIOCA1 P14/TIOCA1 P14/TIOCA1 NC P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0 PE1 PE2 PE3 VSS P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS P15/ TIOCB1/ TCLKC P16/ TIOCA2 P17/ TIOCB2/ TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/ IRQ4 P35/SCK1/ IRQ5 PE0 PE1 PE2 PE3 VSS NC 5 6 NC NC 7 8 9 10 11 12 13 14 15 16 17 18 VSS NC NC NC NC NC NC NC NC NC NC VSS Rev.3.00 Mar. 26, 2007 Page 8 of 772 REJ09B0355-0300 Section 1 Overview Pin No. FP-100B, TFP-100B Mode 1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 Mode 2* PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 VCC PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 1 Pin Name Mode 3* PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 1 Mode 4 PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 Mode 5 PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 A13 A14 A15 Mode 6* PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 VCC PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 1 Mode 7* PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 1 PROM 2 Mode* NC NC NC NC D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 VCC A8 OE A10 A11 A12 A13 A14 A15 Rev.3.00 Mar. 26, 2007 Page 9 of 772 REJ09B0355-0300 Section 1 Overview Pin No. FP-100B, TFP-100B Mode 1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 VSS PA0 PA1 PA2 PA3 P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ AS RD HWR LWR PF2/WAIT/ BREQO/ IRQ2 Mode 2* VSS PA0 PA1 PA2 PA3 P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ AS RD HWR LWR PF2/WAIT/ BREQO/ IRQ2 1 Pin Name Mode 3* VSS PA0 PA1 PA2 PA3 P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ PF6 PF5 PF4 PF3/IRQ3 PF2/IRQ2 1 Mode 4 VSS A16 A17 A18 A19 P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ AS RD HWR LWR PF2/WAIT/ BREQO/ IRQ2 Mode 5 VSS A16 A17 A18 A19 P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ AS RD HWR LWR PF2/WAIT/ BREQO/ IRQ2 Mode 6* VSS PA0/A16 PA1/A17 PA2/A18 PA3/A19 1 Mode 7* VSS PA0 PA1 PA2 PA3 1 PROM 2 Mode* VSS A16 VCC VCC NC NC NC NC VSS VSS NC NC VSS VPP A9 VSS VCC NC NC VSS NC NC NC NC NC CE P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ AS RD HWR LWR PF2/WAIT/ BREQO/ IRQ2 P50/TxD2 P51/RxD2 P52/SCK2 MD0 MD1 P53 WDTOVF MD2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ PF6 PF5 PF4 PF3/IRQ3 PF2/IRQ2 75 PF1/BACK/ PF1/BACK/ PF1/IRQ1 IRQ1 IRQ1 PF1/BACK/ PF1/BACK/ PF1/BACK/ PF1/IRQ1 IRQ1 IRQ1 IRQ1 PGM Rev.3.00 Mar. 26, 2007 Page 10 of 772 REJ09B0355-0300 Section 1 Overview Pin No. FP-100B, TFP-100B Mode 1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Mode 2* 1 Pin Name Mode 3* 1 Mode 4 Mode 5 Mode 6* 1 Mode 7* 1 PROM 2 Mode* NC VCC VCC NC NC NC NC VSS VSS NC NC PF0/BREQ/ PF0/BREQ/ PF0/IRQ0 IRQ0 IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 PF0/BREQ/ PF0/BREQ/ PF0/BREQ/ PF0/IRQ0 IRQ0 IRQ0 IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVSS VSS P20 P21 P22/TMRI0 P22/TMRI0 P22/TMRI0 P22/TMRI0 P22/TMRI0 P22/TMRI0 P22/TMRI0 NC P23/TMCI0 P23/TMCI0 P23/TMCI0 P23/TMCI0 P23/TMCI0 P23/TMCI0 P23/TMCI0 NC P24/TMRI1 P24/TMRI1 P24/TMRI1 P24/TMRI1 P24/TMRI1 P24/TMRI1 P24/TMRI1 NC P25/TMCI1 P25/TMCI1 P25/TMCI1 P25/TMCI1 P25/TMCI1 P25/TMCI1 P25/TMCI1 NC P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/IRQ7 PG2 PG3 PG4/CS0 VCC P10/ TIOCA0 P11/ TIOCB0 P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/IRQ7 PG2 PG3 PG4/CS0 VCC P10/ TIOCA0 P11/ TIOCB0 P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/IRQ7 PG2 PG3 PG4 VCC P10/ TIOCA0 P11/ TIOCB0 P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 VCC P26/TMO0 P27/TMO1 PG0/IRQ6/ ADTRG PG1/IRQ7 PG2 PG3 PG4 VCC NC NC NC NC NC NC NC VCC NC NC P10/ P10/ P10/ P10/ TIOCA0/A20 TIOCA0/A20 TIOCA0/A20 TIOCA0 P11/ P11/ P11/ P11/ TIOCB0/A21 TIOCB0/A21 TIOCB0/A21 TIOCB0 Notes: 1. Cannot be used in the H8S/2240. 2. NC should be left open. Rev.3.00 Mar. 26, 2007 Page 11 of 772 REJ09B0355-0300 Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions. Table 1.3 Pin Functions Pin No. Type Power Symbol VCC FP-100B, TFP-100B 40, 65, 98 I/O Input Name and Function Power supply: All VCC pins should be connected to the system power supply. Ground: All VSS pins should be connected to the system power supply (0 V). Connects to a crystal oscillator. See section 17, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 17, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. VSS 7, 18, 31, 49, 68, 84 Input Clock XTAL 66 Input EXTAL 67 Input 69 Output System clock: Supplies the system clock to an external device. Rev.3.00 Mar. 26, 2007 Page 12 of 772 REJ09B0355-0300 Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B 61, 58, 57 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2245 Group is operating. Except for mode changing, be sure to fix the levels of the mode pins (MD2 to MD0) by pulling them down or pulling them up until the power turns off. MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Operating Mode -- Mode 1 Mode 2* Mode 3* Mode 4 Mode 5 Mode 6* Mode 7* Operating mode MD2 to control MD0 Note: * Cannot be used in the H8S/2240. System control RES 62 Input Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2245 Group. STBY 64 Input BREQ 76 Input BREQO 74 Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. Rev.3.00 Mar. 26, 2007 Page 13 of 772 REJ09B0355-0300 Section 1 Overview Pin No. Type System control Symbol BACK FP-100B, TFP-100B 75 I/O Name and Function Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. Interrupts NMI 63 IRQ7 to 1 IRQ0* Address bus A23 to A0 D15 to D0 CS3 to CS0 AS 94, 93, 13, 12, 73 to 76 2, 1, 100, 99, 53 to 50, 48 to 41, 39 to 32 30 to 19, 17 to 14 94 to 97 70 Input Output Address bus: These pins output an address. I/O Data bus: These pins constitute a bidirectional data bus. Data bus Bus control Output Chip select: Signals for selecting areas 3 to 0. Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. RD 71 HWR 72 LWR 73 WAIT 74 Rev.3.00 Mar. 26, 2007 Page 14 of 772 REJ09B0355-0300 Section 1 Overview Pin No. Type 16-bit timerpulse unit (TPU) Symbol FP-100B, TFP-100B I/O Input I/O Name and Function Clock input D to A: These pins input an external clock. Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. TCLKD to 6, 4, 2, 1 TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 99, 100, 1, 2 3, 4 I/O TIOCA2, TIOCB2 5, 6 I/O 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 91, 92 88, 90 Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins. 87, 89 Input Watchdog timer (WDT) Serial communication interface (SCI)/ Smart Card interface WDTOVF 60 Output Watchdog timer: The counter overflow signal output pin in watchdog timer mode. Output Transmit data (channel 0, 1, 2): Data output pins. Input Receive data (channel 0, 1, 2): Data input pins. Serial clock (channel 0, 1, 2): Clock I/O pins. TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 54, 9, 8 55, 11, 10 56, 13, 12 I/O Rev.3.00 Mar. 26, 2007 Page 15 of 772 REJ09B0355-0300 Section 1 Overview Pin No. Type A/D converter Symbol AN3 to AN0 ADTRG FP-100B, TFP-100B 82 to 79 93 I/O Input Input Name and Function Analog 3 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. This is the power supply pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+5 V). This is the ground pin for the A/D converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+5 V). Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: A 4-bit input port. Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). AVCC 77 Input AVSS 83 Input Vref 78 Input I/O ports P17 to P10 6 to 1, 100, 99 I/O P27 to P20 92 to 85 I/O P35 to P30 13 to 8 I/O P43 to P40 P53 to P50 82 to 79 59, 56 to 54 Input I/O Rev.3.00 Mar. 26, 2007 Page 16 of 772 REJ09B0355-0300 Section 1 Overview Pin No. Type I/O ports Symbol PA3 to 2 PA0* FP-100B, TFP-100B 53 to 50 I/O I/O Name and Function Port A: A 4-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). PB7 to 3 PB0* 48 to 41 I/O PC7 to 3 PC0* 39 to 32 I/O PD7 to 3 PD0* 30 to 23 I/O PE7 to PE0 22 to 19, 17 to 14 I/O PF7 to 4 PF0* 69 to 76 I/O PG4 to PG0 97 to 93 I/O Notes: 1. 2. 3. 4. IRQ3 cannot be used in modes 1, 2, 4, 5, and 6, or in the H8S/2240. Cannot be used in modes 4 and 5 in the H8S/2240. Cannot be used in the H8S/2240. PF6 to PF3 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 17 of 772 REJ09B0355-0300 Section 1 Overview Rev.3.00 Mar. 26, 2007 Page 18 of 772 REJ09B0355-0300 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) Rev.3.00 Mar. 26, 2007 Page 19 of 772 REJ09B0355-0300 Section 2 CPU * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8 x 8-bit register-register multiply: 16 / 8-bit register-register divide: 16 x 16-bit register-register multiply: 32 / 16-bit register-register divide: * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU 20 MHz 600 ns (20-MHz operation) 600 ns (20-MHz operation) 1000 ns (20-MHz operation) 1000 ns (20-MHz operation) 8/16/32-bit register-register add/subtract: 50 ns (20-MHz operation) The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of execution states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, EXR register functions, power-down state, etc., depending on the product. Rev.3.00 Mar. 26, 2007 Page 20 of 772 REJ09B0355-0300 Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev.3.00 Mar. 26, 2007 Page 21 of 772 REJ09B0355-0300 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Maximum 64 kbytes, program and data areas combined Normal mode CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Figure 2.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev.3.00 Mar. 26, 2007 Page 22 of 772 REJ09B0355-0300 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev.3.00 Mar. 26, 2007 Page 23 of 772 REJ09B0355-0300 Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev.3.00 Mar. 26, 2007 Page 24 of 772 REJ09B0355-0300 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev.3.00 Mar. 26, 2007 Page 25 of 772 REJ09B0355-0300 Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) SP CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.5 Stack Structure in Advanced Mode Rev.3.00 Mar. 26, 2007 Page 26 of 772 REJ09B0355-0300 Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2245 Group H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.6 Memory Map Rev.3.00 Mar. 26, 2007 Page 27 of 772 REJ09B0355-0300 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR* T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * This register does not affect operations in the H8S/2245 Group. Figure 2.7 CPU Registers Rev.3.00 Mar. 26, 2007 Page 28 of 772 REJ09B0355-0300 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) * 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Rev.3.00 Mar. 26, 2007 Page 29 of 772 REJ09B0355-0300 Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word) so the least significant PC bit is ignored. (When an instruction is read, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register does not affect operation in the H8S/2245 Group. Bit 7--Trace Bit (T): This bit is reserved. It does not affect operation in the H8S/2245 Group. Bits 6 to 3--Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits are reserved. They do not affect operation in the H8S/2245 Group. Rev.3.00 Mar. 26, 2007 Page 30 of 772 REJ09B0355-0300 Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev.3.00 Mar. 26, 2007 Page 31 of 772 REJ09B0355-0300 Section 2 CPU Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev.3.00 Mar. 26, 2007 Page 32 of 772 REJ09B0355-0300 Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type General Register Data Image 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don't care 4-bit BCD data RnL Don't care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care Byte data RnL 0 LSB MSB Figure 2.10 General Register Data Formats Rev.3.00 Mar. 26, 2007 Page 33 of 772 REJ09B0355-0300 Section 2 CPU Data Type Word data General Register Rn Data Image 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) Rev.3.00 Mar. 26, 2007 Page 34 of 772 REJ09B0355-0300 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data image Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When SP(ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Rev.3.00 Mar. 26, 2007 Page 35 of 772 REJ09B0355-0300 Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM* , STM* 3 5 5 3 1 1 Size BWL WL L B BWL B BWL L BW WL B BWL Types 5 MOVFPE* , MOVTPE* Arithmetic operations ADD, SUB, CMP, NEG 19 ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT 4 8 14 5 9 1 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* , JMP, BSR, JSR, RTS 2 B -- TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- EEPMOV -- Total: 65 types Legend: B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2245 Group. Rev.3.00 Mar. 26, 2007 Page 36 of 772 REJ09B0355-0300 Section 2 CPU 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes @-ERn/@ERn+ @(d:16,ERn) @(d:32,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:32 @aa:8 Rn Data transfer MOV POP, PUSH LDM, STM MOVFPE*, MOVTPE* BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- BWL -- BWL -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Arithmetic ADD, CMP operations SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS BWL BWL -- WL BWL -- B -- -- -- -- -- -- B L B BW BW WL -- -- -- -- -- -- -- B -- BWL -- -- BWL -- AND, OR, XOR BWL BWL -- Logic operations NOT -- BWL -- Shift Bit manipulation Branch Bcc, BSR JMP, JSR RTS -- BWL -- -- -- -- -- B -- -- -- B -- -- -- Rev.3.00 Mar. 26, 2007 Page 37 of 772 REJ09B0355-0300 -- Section 2 CPU Addressing Modes @-ERn/@ERn+ @(d:16,ERn) @(d:32,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:32 @aa:8 Rn System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP -- -- -- B -- B -- -- -- -- -- B B -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Block data transfer BW Legend: B: Byte W: Word L: Longword Note: * Cannot be used in the H8S/2245 Group. Rev.3.00 Mar. 26, 2007 Page 38 of 772 REJ09B0355-0300 -- Section 2 CPU 2.6.3 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in the tables is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.3.00 Mar. 26, 2007 Page 39 of 772 REJ09B0355-0300 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* 1 Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2245 Group. Cannot be used in the H8S/2245 Group. @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. B/W/L MOVFPE MOVTPE POP B B W/L PUSH W/L LDM* STM* 2 L L 2 Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Rev.3.00 Mar. 26, 2007 Page 40 of 772 REJ09B0355-0300 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operation Instructions Size* 1 Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. B/W/L ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W DIVXS B/W CMP B/W/L NEG B/W/L Rev.3.00 Mar. 26, 2007 Page 41 of 772 REJ09B0355-0300 Section 2 CPU Instruction EXTU Size* W/L 1 Function Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( EXTS W/L TAS* 2 B Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Mar. 26, 2007 Page 42 of 772 REJ09B0355-0300 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. Rd Rd Takes the one's complement of general register contents. OR B/W/L XOR B/W/L NOT Note: * B/W/L Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Operations Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. B/W/L B/W/L B/W/L Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Mar. 26, 2007 Page 43 of 772 REJ09B0355-0300 Section 2 CPU Table 2.7 Instruction BSET Bit-Manipulation Instructions Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Rev.3.00 Mar. 26, 2007 Page 44 of 772 REJ09B0355-0300 Section 2 CPU Instruction BXOR Size* B Function C ( BIXOR B BILD B BIST B Rev.3.00 Mar. 26, 2007 Page 45 of 772 REJ09B0355-0300 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Rev.3.00 Mar. 26, 2007 Page 46 of 772 REJ09B0355-0300 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B -- Size refers to the operand size. B: Byte W: Word Rev.3.00 Mar. 26, 2007 Page 47 of 772 REJ09B0355-0300 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L - 1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4 - 1 R4 Until R4 = 0 else next; Transfer a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- Rev.3.00 Mar. 26, 2007 Page 48 of 772 REJ09B0355-0300 Section 2 CPU 2.6.4 Basic Instruction Formats The H8S/2245 Group instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.12 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. Rev.3.00 Mar. 26, 2007 Page 49 of 772 REJ09B0355-0300 Section 2 CPU 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports. The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead of time. See section 2.10.3, Bit Manipulation Instructions, for details. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Modes The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 Rev.3.00 Mar. 26, 2007 Page 50 of 772 REJ09B0355-0300 Section 2 CPU (1) Register Direct--Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Rev.3.00 Mar. 26, 2007 Page 51 of 772 REJ09B0355-0300 Section 2 CPU To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 indicates the accessible absolute address ranges. Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF (6) Immediate--#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Rev.3.00 Mar. 26, 2007 Page 52 of 772 REJ09B0355-0300 Section 2 CPU (8) Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev.3.00 Mar. 26, 2007 Page 53 of 772 REJ09B0355-0300 No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 1 Operand is general register contents. Register direct (Rn) Section 2 CPU op rm rn 2 31 General register contents Don't care 0 31 24 23 Register indirect (@ERn) 0 op r 3 31 General register contents 31 disp 31 Sign extension disp 0 0 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 24 23 0 Rev.3.00 Mar. 26, 2007 Page 54 of 772 REJ09B0355-0300 Don't care 31 General register contents 0 31 24 23 Don't care 0 1, 2, or 4 31 General register contents 31 24 23 Don't care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 Table 2.13 Effective Address Calculation op r 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ op r * Register indirect with pre-decrement @-ERn op r No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 5 31 24 23 H'FFFF abs Don't care 87 Absolute address 0 @aa:8 op @aa:16 31 24 23 abs Don't care 16 15 Sign extension 0 op @aa:24 31 abs 24 23 0 op Don't care @aa:32 31 abs 24 23 Don't care 0 op 6 IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. Rev.3.00 Mar. 26, 2007 Page 55 of 772 REJ09B0355-0300 op Section 2 CPU No. Effective Address Calculation 23 PC contents 0 Addressing Mode and Instruction Format Effective Address (EA) 7 Program-counter relative Section 2 CPU @(d:8, PC)/@(d:16, PC) op 23 Sign extension disp 31 24 23 Don't care 0 disp 0 8 Memory indirect @@aa:8 Rev.3.00 Mar. 26, 2007 Page 56 of 772 REJ09B0355-0300 abs 31 H'000000 abs 87 0 31 24 23 Don't care 15 Memory contents 0 16 15 H'00 0 abs 31 H'000000 31 Memory contents 87 abs 0 31 24 23 Don't care 0 0 * Normal mode op * Advanced mode op Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode etc. See section 18, Power-Down Modes, for details. Figure 2.14 Processing States Rev.3.00 Mar. 26, 2007 Page 57 of 772 REJ09B0355-0300 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with SSBY = 1 SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2.15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11, Watchdog Timer. Rev.3.00 Mar. 26, 2007 Page 58 of 772 REJ09B0355-0300 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.14 Exception Handling Types and Priority Priority High Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is 2 executed* Interrupt End of instruction execution or end of exception-handling 1 sequence* When TRAPA instruction is executed Trap instruction Low Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 2. Trap instruction exception handling is always accepted, in the program execution state. Rev.3.00 Mar. 26, 2007 Page 59 of 772 REJ09B0355-0300 Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Normal mode Note: * Ignored when returning. Advanced mode Figure 2.16 Stack Structure after Exception Handling (Examples) Rev.3.00 Mar. 26, 2007 Page 60 of 772 REJ09B0355-0300 Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts except for internal operations. There is one bus masters other than the CPU -- the data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 18, Power-Down Modes. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Rev.3.00 Mar. 26, 2007 Page 61 of 772 REJ09B0355-0300 Section 2 CPU 2.9 2.9.1 Basic Timing Overview The H8S/2000 CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. Bus cycle T1 Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.17 On-Chip Memory Access Cycle Rev.3.00 Mar. 26, 2007 Page 62 of 772 REJ09B0355-0300 Section 2 CPU Bus cycle T1 Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2.18 Pin States during On-Chip Memory Access Rev.3.00 Mar. 26, 2007 Page 63 of 772 REJ09B0355-0300 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states. Bus cycle T1 T2 Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.19 On-Chip Supporting Module Access Cycle Rev.3.00 Mar. 26, 2007 Page 64 of 772 REJ09B0355-0300 Section 2 CPU Bus cycle T1 T2 Unchanged Address bus AS RD HWR, LWR High High High Data bus High-impedance state Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. Rev.3.00 Mar. 26, 2007 Page 65 of 772 REJ09B0355-0300 Section 2 CPU 2.10 2.10.1 Usage Notes TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.2 STM/LDM Instruction With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot be used as a register that allows save (STM) or restore (LDM) operation. With a single STM or LDM instruction, two to four registers can be saved or restored. The available registers are as follows: For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5 For three registers: ER0 to ER2, or ER4 to ER6 For four registers: ER0 to ER3 For the Renesas Technology H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7 is not created. 2.10.3 Bit Manipulation Instructions When a register that includes write-only bits is manipulated by a bit manipulation instruction, there are cases where the bits manipulated are not manipulated correctly or bits unrelated to the bits manipulated are changed. When a register containing write-only bits is read, the value read is either a fixed value or an undefined value. This means that the bit manipulation instructions that use the value of bits read in their operation (BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, and BILD) will not perform correct bit operations. Also, bit manipulation instructions that perform a write operation on the data read after the calculation (BSET, BCLR, BNOT, BST, and BIST) may change bits unrelated to the bits manipulated. Thus extreme care is required when performing bit manipulation instructions on registers that include write-only bits. Rev.3.00 Mar. 26, 2007 Page 66 of 772 REJ09B0355-0300 Section 2 CPU The BSET, BCLR, BNOT, BST, and BIST instructions perform their operations in the following order. 1. Read the data in byte units 2. Perform the bit manipulation operation according to the instruction on the data read 3. Write the data back in byte units Example: Using the BCLR instruction to clear only bit 4 in the port 1 P1DDR register. The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins. Reading this register is invalid. When read, the values returned are undefined. Here we present an example in which P14 is specified to be an input port using the BCLR instruction. Currently, P17 to P14 are set to be output pins and P13 to P10 are set to be input pins. At this point, the value of P1DDR is H'F0. P17 I/O P1DDR Output 1 P16 Output 1 P15 Output 1 P14 Output 1 P13 Input 0 P12 Input 0 P11 Input 0 P10 Input 0 To switch P14 from the Output pin to the input pin function, the value of P1DDR bit 4 must be changed from 1 to 0 (H'F0 H'E0). Here we assume that the BCLR instruction is used to clear P1DDR bit 4. BCLR #4,@P1DDR However if a bit manipulation instruction of the type shown above is used on P1DDR, which is a write-only register, the following problem may occur. Although the first thing that happens is that data is read from P1DDR in byte units, the value read at this time is undefined. An undefined value is a value that is either 0 or 1 in the register but reads out as an arbitrary value whose relationship to the actual value is unknown. Since the P1DDR bits are all write-only bits, every bit reads out as an undefined value. Although the actual value of P1DDR at this point is H'F0, assume that bit 3 becomes a 1 here, and the value read out is H'F8. P17 I/O P1DDR Read value Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 1 P13 Input 0 1 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Rev.3.00 Mar. 26, 2007 Page 67 of 772 REJ09B0355-0300 Section 2 CPU The bit manipulation operation is performed on this value that was read. In this example, bit 4 will be cleared for H'F8. P17 I/O P1DDR After bit manipulation Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 0 P13 Input 0 1 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 After the bit manipulation operation, this data will be written to P1DDR, and the BCLR instruction completes. P17 I/O P1DDR Write value Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Input 0 0 P13 Output 1 1 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Although the instruction was expected to write H'E0 back to P1DDR, it actually wrote H'E8, and P13, which was expected to be an input pin, is changed to function as an output pin. While this section described the case where P13 was read out as a 1, since the values read are undefined when P17 to P10 are read, when this bit manipulation instruction completes, bits that were 0 may be changed to 1, and bits that were 1 may be changed to 0. To avoid this sort of problem, see section 2.10.4, Access Methods for Registers with Write-Only Bits, for methods for modifying registers that include write-only bits. Also note that it is possible to use the BCLR instruction to clear to 0 flags in internal I/O registers. In this case, if it is clear from the interrupt handler or other information that the corresponding flag is set to 1, then there is no need to read the value of the corresponding flag in advance. 2.10.4 Access Methods for Registers with Write-Only Bits Undefined values will be read out if a data transfer instruction is executed for a register that includes write-only bits, or if a bit manipulation instruction is executed for a register that includes write-only bits. To avoid reading undefined values, use methods such as those shown below to access registers that include write-only bits. The basic method for writing to a register that includes write-only bits is to create a work area in internal RAM or other memory area and first write the data to that area. Then, perform the desired access operation for that memory and finally write that data to the register that includes write-only bits. Rev.3.00 Mar. 26, 2007 Page 68 of 772 REJ09B0355-0300 Section 2 CPU Write data to the work area Initial value write Write the work area data to the register that includes write-only bits Access the work area data (data transfer and bit manipulation instructions can be used) Modifying the value of a register that includes write-only bits Write the work area data to the register that includes write-only bits Figure 2.21 Flowchart for Access Methods for Registers That Include Write-Only Bits Example: To clear only bit 4 in the port 1 P1DDR The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins. Reading this register is invalid. When read, the values returned are undefined. Here we present an example in which P14 is specified to be an input port using the BCLR instruction. First, we write the initial value H'F0 written to P1DDR to the work area in RAM (RAM0). MOV.B MOV.B MOV.B #H'F0, R0L, R0L, R0L @PAM0 @P1DDR P17 I/O P1DDR RAM0 Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 1 P13 Input 0 0 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Rev.3.00 Mar. 26, 2007 Page 69 of 772 REJ09B0355-0300 Section 2 CPU To switch P14 from being an output pin to being an input pin, we must change the value of P1DDR bit 4 from 1 to 0 (H'F0 H'E0). Here, were execute a BCLR instruction for RAM0. BCLR I/O P1DDR RAM0 #4, @RAM0 P17 Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 0 P13 Input 0 0 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Since RAM0 can be read and written, when the bit manipulation instruction is executed, only bit 4 in RAM0 is cleared. Then we write this RAM0 value to P1DDR. MOV.B MOV.B @RAM0, R0L, P17 I/O P1DDR RAM0 Output 1 1 R0L @P1DDR P16 Output 1 1 P15 Output 1 1 P14 Input 0 0 P13 Input 0 0 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 If this procedure is used to write registers that include write-only bits, programs can be written without depending on the type of the instructions used. Rev.3.00 Mar. 26, 2007 Page 70 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection Except for the H8S/2240, all H8S/2245 Group products have seven operating modes (modes 1 to 7). The H8S/2240 has three operating modes (modes 1, 4, and 5). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode 0 1 2* 3* 4 5 6* 7* 1 1 0 1 MCU Operating Mode Selection CPU Operating Mode -- Normal External Data Bus Description -- On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode Advanced On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode Disabled On-chip ROM -- Disabled Enabled Initial Width -- 8 bits 8 bits -- 16 bits 8 bits Enabled 8 bits -- Max. Width -- 16 bits 16 bits -- 16 bits 16 bits 16 bits -- MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 1 Note: * Cannot be used in the H8S/2240. The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2245 Group actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. Rev.3.00 Mar. 26, 2007 Page 71 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The H8S/2245 Group can be used only in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The H8S/2245 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2245 Group. Table 3.2 summarizes these registers. Table 3.2 Name Mode control register System control register Note: * Register Configuration Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'01 Address* H'FF3B H'FF39 Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 72 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 -- 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Initial value : R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2245 Group. Bit 7--Reserved: Read-only bit, always read as 1. Bits 6 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. 3.2.2 Bit System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 -- 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, the detected edge for NMI, and enable or disable the on-chip RAM. SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Reserved: This bit can be read or written, but does not affect operation. Rev.3.00 Mar. 26, 2007 Page 73 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Bit 6--Reserved: Read-only bit, always read as 0. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 1 -- -- Description Control of interrupts by I bit (Initial value) Control of interrupts by I bit, U bit, and ICR Setting prohibited Setting prohibited Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bits 2 and 1--Reserved: Read-only bits, always read as 0. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit should not be cleared to 0. Rev.3.00 Mar. 26, 2007 Page 74 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.2 Mode 2 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set immediately after a reset. Ports B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. The amount of on-chip ROM that can be used on the H8S/2246, H8S/2245, H8S/2244, and H8S/2243 is limited to 56 kbytes. Note: Mode 2 cannot be used in the H8S/2240. 3.3.3 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. The amount of on-chip ROM that can be used on the H8S/2246, H8S/2245, H8S/2244, and H8S/2243 is limited to 56 kbytes. Note: Mode 3 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 75 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P10 function as input ports immediately after a reset. They can each be set to output address use by setting the corresponding bits in the data direction register (DDR) to 1. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.5 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D functions as a data bus, and part of port F carries bus control signals. Pins P13 to P10 function as input ports immediately after a reset. They can each be set to output address use by setting the corresponding bits in the data direction register (DDR) to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A, B, and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. Note: Mode 6 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 76 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes 3.3.7 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Note: Mode 7 cannot be used in the H8S/2240. 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Port Port 1 Port A Port B Port C Port D Port E Port F PF7 PF6 to PF3 PF2 to PF0 P13 to P10 PA3 to PA0 Pin Functions in Each Mode Mode 1 P* /T P A A D P* /D P/C* C P* /C 1 1 1 1 Mode 2* Mode 3* Mode 4 P* /T P P* /A P* /A D P* /D P/C* C P* /C 1 1 1 1 1 1 2 2 Mode 5 P* /T/A A A A D 1 Mode 6* Mode 7* P* /T/A P* /A P* /A P* /A D 1 1 1 1 2 2 P* /T P P P P P P* /C P 1 1 P* /T/A A A A D P/D* P/C* C P* /C 1 1 1 1 P* /T P P P P 1 P* /D P/C* C P* /C 1 1 1 P* /D P/C* C P* /C 1 1 1 P P* /C P 1 Legend: P: I/O port T: Timer I/O A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. After reset 2. Cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 77 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes 3.5 Memory Map in Each Operating Mode The H8S/2246, H8S/2245, H8S/2244, H8S/2243, H8S/2242, H8S/2241, and H8S/2240 memory maps are shown in figures 3.1 to 3.7. The address space is 64 kbytes in modes 1 to 3 (normal modes), and 16 Mbytes in modes 4 to 7 (advanced modes). The on-chip ROM size is 128 kbytes in the H8S/2246 and H8S/2245, and 64 kbytes in the H8S/2244 and H8S/2243, but only 56 kbytes are available in modes 2 and 3 (normal modes). The on-chip ROM size in the H8S/2242 and H8S/2241 is 32 kbytes. The address space is divided into eight areas for modes 4 to 6. For details, see section 6, Bus Controller. Rev.3.00 Mar. 26, 2007 Page 78 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 On-chip ROM External address space On-chip ROM H'DFFF H'E000 H'E400 On-chip RAM* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space H'DFFF External address space H'E400 On-chip RAM* On-chip RAM H'FBFF External address space H'E400 H'FBFF H'FC00 H'FE3F H'FF08 Internal I/O registers External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 H8S/2246 Memory Map in Each Operating Mode Rev.3.00 Mar. 26, 2007 Page 79 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address H'FFFE3F space Internal I/O registers H'FFFF08 External address space H'01FFFF H'020000 External address space H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address H'FFFE3F space Internal I/O registers H'FFFF08 External address space H'01FFFF H'FFDC00 On-chip RAM H'FFFBFF H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. This area is reserved when the EAE bit in BCRL is set to 1, and on-chip ROM when the EAE bit is cleared to 0. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 H8S/2246 Memory Map in Each Operating Mode (cont) Rev.3.00 Mar. 26, 2007 Page 80 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 External address space On-chip ROM On-chip ROM H'DFFF H'E000 H'E400 H'EC00 On-chip RAM* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space H'DFFF External address space Reserved area* H'EC00 On-chip RAM* On-chip RAM H'FBFF External address space Reserved area* H'E400 H'EC00 H'FBFF H'FC00 H'FE3F H'FF08 Internal I/O registers External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.2 H8S/2245 Memory Map in Each Operating Mode Rev.3.00 Mar. 26, 2007 Page 81 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'FFDC00 Reserved area*3 H'01FFFF H'020000 External address space H'FFDC00 Reserved area*3 H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'01FFFF H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFEC00 H'FFFBFF On-chip RAM H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. This area is reserved when the EAE bit in BCRL is set to 1, and on-chip ROM when the EAE bit is cleared to 0. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.2 H8S/2245 Memory Map in Each Operating Mode (cont) Rev.3.00 Mar. 26, 2007 Page 82 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 External address space On-chip ROM On-chip ROM H'DFFF H'E000 H'E400 On-chip RAM* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space H'DFFF External address space H'E400 On-chip RAM* On-chip RAM H'FBFF External address space H'E400 H'FBFF H'FC00 H'FE3F H'FF08 Internal I/O registers External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.3 H8S/2244 Memory Map in Each Operating Mode Rev.3.00 Mar. 26, 2007 Page 83 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 H'00FFFF External address space/reserved area*1 H'FFDC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'01FFFF H'020000 External address space H'FFDC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFDC00 On-chip RAM H'FFFBFF H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is reserved. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.3 H8S/2244 Memory Map in Each Operating Mode (cont) Rev.3.00 Mar. 26, 2007 Page 84 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 External address space On-chip ROM On-chip ROM H'DFFF H'E000 H'E400 H'EC00 On-chip RAM* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space H'DFFF External address space Reserved area* H'EC00 On-chip RAM* On-chip RAM H'FBFF External address space Reserved area* H'E400 H'EC00 H'FBFF H'FC00 H'FE3F H'FF08 Internal I/O registers External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.4 H8S/2243 Memory Map in Each Operating Mode Rev.3.00 Mar. 26, 2007 Page 85 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'00FFFF H'010000 H'00FFFF External address space/reserved area*1 H'FFDC00 Reserved area*2 H'01FFFF H'020000 External address space H'FFDC00 Reserved area*2 H'FFEC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFEC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFEC00 H'FFFBFF On-chip RAM H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is reserved. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.4 H8S/2243 Memory Map in Each Operating Mode (cont) Rev.3.00 Mar. 26, 2007 Page 86 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'7FFF H'8000 H'7FFF Reserved area H'DFFF H'E000 H'E400 On-chip RAM* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space External address space H'E400 On-chip RAM* On-chip RAM H'FBFF External address space H'E400 H'FBFF H'FC00 H'FE3F H'FF08 Internal I/O registers External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 H8S/2242 Memory Map in Each Operating Mode Rev.3.00 Mar. 26, 2007 Page 87 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'007FFF H'008000 Reserved area External address space H'00FFFF H'010000 H'007FFF External address space/reserved area*1 H'FFDC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'01FFFF H'020000 External address space H'FFDC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFDC00 On-chip RAM H'FFFBFF H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is reserved. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 H8S/2242 Memory Map in Each Operating Mode (cont) Rev.3.00 Mar. 26, 2007 Page 88 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'7FFF H'8000 H'7FFF Reserved area H'DFFF H'E000 H'E400 H'EC00 On-chip RAM* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space External address space Reserved area* H'EC00 On-chip RAM* On-chip RAM H'FBFF External address space Reserved area* H'E400 H'EC00 H'FBFF H'FC00 H'FE3F H'FF08 Internal I/O registers External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.6 H8S/2241 Memory Map in Each Operating Mode Rev.3.00 Mar. 26, 2007 Page 89 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'007FFF H'008000 Reserved area External address space H'007FFF H'00FFFF H'010000 External address space/reserved area*1 H'FFDC00 Reserved area*2 H'01FFFF H'020000 External address space H'FFDC00 Reserved area*2 H'FFEC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFEC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFEC00 H'FFFBFF On-chip RAM H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is reserved. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.6 H8S/2241 Memory Map in Each Operating Mode (cont) Rev.3.00 Mar. 26, 2007 Page 90 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space External address space H'E400 H'EC00 Reserved area* H'FFDC00 On-chip RAM* Reserved area* H'FBFF H'FC00 External address space H'FE3F Internal I/O registers H'FF08 External address space H'FFEC00 On-chip RAM* H'FFFBFF H'FFFC00 External address H'FFFE3F space Internal I/O registers H'FFFF08 External address space H'FF28 Internal I/O registers H'FFFF H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.7 H8S/2240 Memory Map in Each Operating Mode (Modes 1, 4, and 5 Only) Rev.3.00 Mar. 26, 2007 Page 91 of 772 REJ09B0355-0300 Section 3 MCU Operating Modes Rev.3.00 Mar. 26, 2007 Page 92 of 772 REJ09B0355-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. See appendix D.1, Port States in Each Mode. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Priority High Exception Handling Types and Priority Exception Handling Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has 1 been issued* 2 Low Trap instruction (TRAPA)* Started by execution of a trap instruction (TRAPA) Notes: 1. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 2. Trap instruction exception handling requests are accepted at all times in program execution state. 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. Rev.3.00 Mar. 26, 2007 Page 93 of 772 REJ09B0355-0300 Section 4 Exception Handling 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Power-on reset Manual reset Exception sources External interrupts: NMI, IRQ7 to IRQ0 Interrupts Internal interrupts: 34 interrupt sources in on-chip supporting modules Trap instruction Figure 4.1 Exception Sources In modes 6 and 7, the on-chip ROM available for use on the H8S/2246 and H8S/2245 after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 128-kbyte area comprising addresses H'000000 to H'01FFFF to be used for the on-chip ROM. Rev.3.00 Mar. 26, 2007 Page 94 of 772 REJ09B0355-0300 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Power-on reset Manual reset Reserved for system use Vector Number 0 1 2 3 4 5 6 Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0006 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00B6 to H'00B7 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'016C to H'016F External interrupt NMI 7 8 9 10 11 Trap instruction (4 sources) Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 2 16 17 18 19 20 21 22 23 24 91 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. Rev.3.00 Mar. 26, 2007 Page 95 of 772 REJ09B0355-0300 Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2245 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The level of the NMI pin at reset determines whether the type of reset is a power-on reset or a manual reset. The H8S/2245 Group can also be reset by overflow of the watchdog timer. For details see section 11, Watchdog Timer. 4.2.2 Reset Types A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4.3. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip peripheral modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4.3 Reset Types Reset Transition Conditions Type Power-on reset Manual reset NMI High Low RES Low Low CPU Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except for bus controller and I/O ports Rev.3.00 Mar. 26, 2007 Page 96 of 772 REJ09B0355-0300 Section 4 Exception Handling A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. 4.2.3 Reset Sequence The H8S/2245 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2245 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2245 Group during operation, hold the RES pin low for at least 20 states. See appendix D.1, Port States in Each Mode. When the RES pin goes high after being held low for the necessary time, the H8S/2245 Group starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. Vector Internal Fetch of first program fetch processing instruction RES Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (3) (4) (2) (1) (3) High (4) Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction Figure 4.2 Reset Sequence (Modes 2 and 3) Rev.3.00 Mar. 26, 2007 Page 97 of 772 REJ09B0355-0300 Section 4 Exception Handling Vector fetch Internal Fetch of first processing program instruction * * RES Address bus RD HWR, LWR D15 to D0 * (1) (3) (5) High (2) (4) (6) (1) (3) (2) (4) (5) (6) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 4) 4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCR is initialized to H'3FFF and all modules except the DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Rev.3.00 Mar. 26, 2007 Page 98 of 772 REJ09B0355-0300 Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 34 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to three priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) Internal interrupts WDT* (1) TPU (13) 8-bit timer (6) SCI (12) DTC (1) A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts Rev.3.00 Mar. 26, 2007 Page 99 of 772 REJ09B0355-0300 Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR after execution of trap instruction exception handling. Table 4.4 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 Legend: 1: Set to 1 --: Retains value prior to execution. I 1 1 UI -- 1 Rev.3.00 Mar. 26, 2007 Page 100 of 772 REJ09B0355-0300 Section 4 Exception Handling 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes) SP CCR PC (24 bits) Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes) Rev.3.00 Mar. 26, 2007 Page 101 of 772 REJ09B0355-0300 Section 4 Exception Handling 4.6 Notes on Use of the Stack When accessing word data or longword data, the H8S/2245 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAPA instruction executed MOV.B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd Rev.3.00 Mar. 26, 2007 Page 102 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2245 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. * DTC control DTC activation is performed by means of interrupts. Rev.3.00 Mar. 26, 2007 Page 103 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I, UI Interrupt request Vector number CPU Internal interrupt request WOVI to TEI CCR ICR Interrupt controller Legend: ISCR IER ISR ICR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt control register : System control register Figure 5.1 Block Diagram of Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 104 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected IRQ7 to IRQ0 Input 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt control register A Interrupt control register B Interrupt control register C Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR ICRA ICRB ICRC R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address* H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC0 H'FEC1 H'FEC2 1 Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 105 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 -- 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 1 -- -- Description Interrupts are controlled by I bit (Initial value) Interrupts are controlled by I and UI bits and ICR Setting prohibited Setting prohibited Bit 3--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) Rev.3.00 Mar. 26, 2007 Page 106 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.2.2 Bit Interrupt Control Registers A to C (ICRA to ICRC) : 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W 3 ICR3 0 R/W 2 ICR2 0 R/W 1 ICR1 0 R/W 0 ICR0 0 R/W Initial value: R/W : The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI. The correspondence between ICR settings and interrupt sources is shown in table 5.3. The ICR registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--Interrupt Control Level (ICRn): Bit n ICRn 0 1 Description The corresponding interrupt requests have priority level 0 (low priority) The corresponding interrupt requests have priority level 1 (high priority) (Initial value) Note: n = 7 to 0 Table 5.3 Correspondence between Interrupt Sources and ICR Settings Bits Register 7 ICRA ICRB ICRC IRQ0 -- 6 IRQ1 5 IRQ2 IRQ3 4 IRQ4 IRQ5 3 IRQ6 IRQ7 2 DTC 1 0 Watchdog -- timer -- -- -- A/D TPU TPU TPU -- converter channel 0 channel 1 channel 2 8-bit timer 8-bit timer -- channel 0 channel 1 SCI SCI SCI -- channel 0 channel 1 channel 2 Rev.3.00 Mar. 26, 2007 Page 107 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.2.3 Bit IRQ Enable Register (IER) : 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value: R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (Initial value) Note: n = 7 to 0 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W : ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W : Rev.3.00 Mar. 26, 2007 Page 108 of 772 REJ09B0355-0300 Section 5 Interrupt Controller The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value: R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 109 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Bits 7 to 0--IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] * * * * 1 * * * * (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When IRQn interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When DTC is activated by IRQn interrupt while DISEL bit of MRB in DTC is 0. When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) [Setting conditions] Note: n = 7 to 0 Rev.3.00 Mar. 26, 2007 Page 110 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (34 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2245 Group from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt control level can be set with ICR. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 7 to 0 S R Q IRQn interrupt request Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. Rev.3.00 Mar. 26, 2007 Page 111 of 772 REJ09B0355-0300 Section 5 Interrupt Controller IRQn input pin IRQnF Note: n = 7 to 0 Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. Interrupt request flags IRQ7 to IRQ0 are set when the setting condition is met, regardless of the IER setting, and therefore only the necessary flags should be checked. 5.3.2 Internal Interrupts There are 34 sources for internal interrupts from on-chip supporting modules. * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt control level can be set by means of ICR. * The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DTC is activated by an interrupt, it is not affected by the interrupt control mode and interrupt mask bits. 5.3.3 Interrupt Exception Handling Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Rev.3.00 Mar. 26, 2007 Page 112 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source External pin Vector Address* Vector Number 7 16 17 18 19 20 21 22 23 DTC Watchdog timer -- -- 24 25 26 27 28 29 30 31 32 33 34 35 36 -- 37 38 39 Normal Mode H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C ICRB5 ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 ICRB7 ICRB6 ICR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) Reserved ADI (A/D conversion end) Reserved A/D -- TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved TPU channel 0 Low Rev.3.00 Mar. 26, 2007 Page 113 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Origin of Interrupt Source TPU channel 1 Vector Address* Vector Number 40 41 42 43 TPU channel 2 44 45 46 47 -- 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Normal Mode H'0050 H'0052 H'0054 H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC ICRB2 ICRB3 ICR ICRB4 Priority High Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) Reserved -- ICRB1 -- ICRB0 Low Rev.3.00 Mar. 26, 2007 Page 114 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Origin of Interrupt Source 8-bit timer channel 0 Vector Address* Vector Number 64 65 66 -- 8-bit timer channel 1 67 68 69 70 -- -- 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Normal Mode H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C Low ICRC2 ICRC3 ICRC5 ICRC6 ICR ICRC7 Priority High Interrupt Source CMIA0 (compare match A) CMIB0 (compare match B) OVI0 (overflow 0) Reserved CMIA1 (compare match A) CMIB1 (compare match B) OVI1 (overflow 1) Reserved Reserved ERI0 (receive error 0) SCI RXI0 (reception completed 0) channel 0 TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) SCI RXI1 (reception completed 1) channel 1 TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) SCI RXI2 (reception completed 2) channel 2 TXI2 (transmit data empty 2) TEI2 (transmission end 2) Note: * ICRC4 Lower 16 bits of the start address. Rev.3.00 Mar. 26, 2007 Page 115 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2245 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated by the I and UI bits in the CPU's CCR. Table 5.5 Interrupt Control Modes Interrupt Mask Bits Description I Interrupt mask control is performed by the I bit. Priority can be set with ICR. 1 1 ICR I, UI 3-level interrupt mask control is performed by the I and UI bits. Priority can be set with ICR. SYSCR Interrupt Priority Control Mode INTM1 INTM0 Setting Registers 0 0 0 ICR Rev.3.00 Mar. 26, 2007 Page 116 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. I ICR UI Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control and 3-Level Control Interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 1 0 1 Legend: *: Don't care UI * * * 0 1 Selected Interrupts All interrupts (control level 1 has priority) NMI interrupts All interrupts (control level 1 has priority) NMI and control level 1 interrupts NMI interrupts Rev.3.00 Mar. 26, 2007 Page 117 of 772 REJ09B0355-0300 Section 5 Interrupt Controller (2) Default Priority Determination When an interrupt is selected its priority is determined and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the table 5.4 and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.7 shows operations and control signal functions in each interrupt control mode. Table 5.7 Operations and Control Signal Functions in Each Interrupt Control Mode Setting INTM1 INTM0 Interrupt Acceptance Control 3-Level Control I UI ICR Default Priority Determination Interrupt Control Mode 0 1 0 0 1 IM IM -- IM PR PR Legend: : Interrupt operation control performed IM: Used as interrupt mask bit PR: Sets priority. --: Not used. Rev.3.00 Mar. 26, 2007 Page 118 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.3.00 Mar. 26, 2007 Page 119 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes No NMI? No Control level 1 interrupt? Yes No IRQ0? No Hold pending No IRQ0? Yes No IRQ1? Yes Yes IRQ1? No Yes TEI2? Yes TEI2? Yes I = 0? Yes No Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.3.00 Mar. 26, 2007 Page 120 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU's CCR, and ICR. * Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. * Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00 are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control level 1 and other interrupts to control level 0), the situation is as follows: * When I = 0, all interrupts are enabled (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 ...) * When I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 interrupts are enabled * When I = 1 and UI = 1, only NMI interrupts are enabled Figure 5.6 shows the state transitions in these cases. I0 All interrupts enabled I 1, UI 0 Only NMI, IRQ2, and IRQ3 interrupts enabled I0 Exception handling execution or I 1, UI 1 UI 0 Exception handling execution or UI 1 Only NMI interrupts enabled Figure 5.6 Example of State Transitions in Interrupt Control Mode 1 Figure 5.7 shows a flowchart of the interrupt acceptance operation in this case. Rev.3.00 Mar. 26, 2007 Page 121 of 772 REJ09B0355-0300 Section 5 Interrupt Controller [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] The I bit is then referenced. If the I bit is cleared to 0, it is not affected by the UI bit. An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bits is set to 1 and the UI bit is cleared to 0. When both the I bit and the UI bit are set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.3.00 Mar. 26, 2007 Page 122 of 772 REJ09B0355-0300 Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI? No Control level 1 interrupt? Yes No No IRQ1? Yes TEI2? Yes No Hold pending No IRQ0? Yes IRQ1? Yes TEI2? Yes No IRQ0? Yes I = 0? Yes No I = 0? No Yes No UI = 0? Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev.3.00 Mar. 26, 2007 Page 123 of 772 REJ09B0355-0300 5.4.4 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch Interrupt level determination Wait for end of instruction Section 5 Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 124 of 772 REJ09B0355-0300 (1) (3) (5) (7) (9) (11) (13) Interrupt request signal Internal address bus Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (4) (6) (8) (10) (12) (14) Internal data bus Figure 5.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.8 Interrupt Exception Handling (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2245 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.8 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.8 are explained in table 5.9. Table 5.8 Interrupt Response Times Normal Mode No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* 1 Advanced Mode INTM1 = 0 3 1 to 19+2*SI 2*SK 2*SI 2*SI 2 12 to 32 INTM1 = 0 3 1 to 19+2*SI 2*SK SI 2*SI 4 Number of wait states until executing 2 instruction ends* PC, CCR stack save Vector fetch Instruction fetch* 3 Internal processing* 2 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.9 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus 2-State Access 2 3-State Access 3+m Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6+2m Legend: m: Number of wait states in an external device access. Rev.3.00 Mar. 26, 2007 Page 125 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5.9 shows and example in which the CMIEA bit in 8-bit timer TCR is cleared to 0. The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TCR write cycle by CPU CMIA exception handling Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.9 Contention between Interrupt Generation and Disabling Rev.3.00 Mar. 26, 2007 Page 126 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.5.5 IRQ Interrupt When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In software standby mode, the input is accepted asynchronously. For details on the input conditions, see section 19.4.2, Control Signal Timing. Rev.3.00 Mar. 26, 2007 Page 127 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.5.6 NMI Interrupt Usage Notes The NMI interrupt is part of the exception processing performed cooperatively by the LSI's internal interrupt controller and the CPU when the system is operating normally under the specified electrical conditions. No operations, including NMI interrupts, are guaranteed when operation is not normal (runaway status) due to software problems or abnormal input to the LSI's pins. In such cases, the LSI may be restored to the normal program execution state by applying an external reset. 5.6 5.6.1 DTC Activation by Interrupt Overview The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 7, Data Transfer Controller. Rev.3.00 Mar. 26, 2007 Page 128 of 772 REJ09B0355-0300 Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.10 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, UI Interrupt controller Figure 5.10 Interrupt Control for DTC 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCEA to DTCEF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. Rev.3.00 Mar. 26, 2007 Page 129 of 772 REJ09B0355-0300 Section 5 Interrupt Controller (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.10 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCEA to DTCEF in the DTC and the DISEL bit of MRB in the DTC. Table 5.10 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care Interrupt Source Selection/Clearing Control DTC X X CPU (4) Usage Note SCI and A/D converter interrupt sources are cleared when the appropriate DTC register is read or written to, and are independent of the DISEL bit. Rev.3.00 Mar. 26, 2007 Page 130 of 772 REJ09B0355-0300 Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The H8S/2245 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and the data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units In advanced mode, manages the external space as 8 areas of 128-kbytes/2-Mbytes In normal mode, manages the external space as a single area Bus specifications can be set independently for each area Burst ROM interface can be set * Basic bus interface Chip select (CS0 to CS3) can be output for areas 0 to 3 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 1-state or 2-state burst access can be selected * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, and DTC * Other features External bus release function Rev.3.00 Mar. 26, 2007 Page 131 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS3 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Bus controller Internal data bus Internal control signals Bus mode signal WAIT Wait controller WCRH WCRL CPU bus request signal Bus arbiter DTC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal Legend: ABWCR: ASTCR: WCRH: WCRL: BCRH: BCRL: Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Figure 6.1 Block Diagram of Bus Controller Rev.3.00 Mar. 26, 2007 Page 132 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Name Address strobe Read High write Bus Controller Pins Symbol AS RD HWR I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected. Strobe signal indicating that area 2 is selected. Strobe signal indicating that area 3 is selected. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released. Low write LWR Output Chip select 0 Chip select 1 Chip select 2 Chip select 3 Wait Bus request Bus request acknowledge Bus request output CS0 CS1 CS2 CS3 WAIT BREQ BACK BREQO Output Output Output Output Input Input Output Output Rev.3.00 Mar. 26, 2007 Page 133 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL R/W R/W R/W R/W R/W R/W R/W Power-On Reset H'FF/H'00* H'FF H'FF H'FF H'D0 H'3C 2 Manual Reset Retained Retained Retained Retained Retained Retained Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 1 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. Rev.3.00 Mar. 26, 2007 Page 134 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.2 6.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 1, 2, 3, 5, 6, 7 Initial value : R/W Mode 4 Initial value : R/W : 0 R/W : 1 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1, 2, 3, and 5, 6, 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode, only part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access Note: n = 7 to 0 Rev.3.00 Mar. 26, 2007 Page 135 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. In normal mode, only part of area 0 is enabled, and the AST0 bit selects whether external space is to be designated for 2-state access or 3-state access. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) Note: n = 7 to 0 Rev.3.00 Mar. 26, 2007 Page 136 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area is 0 is enabled, and bits W01 and W00 select the number of program wait states for the external space. The settings of bits W71, W70 to W11, and W10 have no effect on operation. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Rev.3.00 Mar. 26, 2007 Page 137 of 772 REJ09B0355-0300 Section 6 Bus Controller Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) Rev.3.00 Mar. 26, 2007 Page 138 of 772 REJ09B0355-0300 Section 6 Bus Controller (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Rev.3.00 Mar. 26, 2007 Page 139 of 772 REJ09B0355-0300 Section 6 Bus Controller Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) Rev.3.00 Mar. 26, 2007 Page 140 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 -- 0 (R/W) 1 -- 0 (R/W) 0 -- 0 (R/W) BRSTRM BRSTS1 BRSTS0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas. Idle cycle inserted in case of successive external read cycles in different areas. (Initial value) Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles. Idle cycle inserted in case of successive external read and external write cycles. (Initial value) Rev.3.00 Mar. 26, 2007 Page 141 of 772 REJ09B0355-0300 Section 6 Bus Controller Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0--Reserved: Only 0 should be written to these bits. Rev.3.00 Mar. 26, 2007 Page 142 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 -- 1 (R/W) 3 -- 1 (R/W) 2 ASS 1 R/W 1 -- 0 (R/W) 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus release state protocol, selection of the area partition unit and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports. (Initial value) External bus release is enabled. Bit 6--BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access. Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO can be used as I/O port. BREQO output enabled. (Initial value) Rev.3.00 Mar. 26, 2007 Page 143 of 772 REJ09B0355-0300 Section 6 Bus Controller Bit 5--External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode. Bit 5 EAE 0 1 Note: * Description Addresses H'010000 to H'01FFFF are in on-chip ROM (H8S/2246 and H8S/2245) or a reserved area* (H8S/2244, H8S/2243, H8S/2242, and H8S/2241). Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode). (Initial value) Reserved areas should not be accessed. Bits 4 and 3--Reserved: Only 1 should be written to these bits. Bit 2--Area Partition Unit Select (ASS): Selects the area partition unit. Bit 2 ASS 0 1 Description Area partition unit is 128 kbytes (1 Mbit) Area partition unit is 2 Mbytes (16 Mbits) (Initial value) Bit 1--Reserved: Only 0 should be written to this bit. Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 144 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.3 6.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 128-kbyte or 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS3) can be output for areas 0 to 3. H'000000 H'01FFFF H'020000 H'03FFFF H'040000 H'05FFFF H'060000 H'07FFFF H'080000 H'09FFFF H'0A0000 H'0BFFFF H'0C0000 H'0DFFFF H'0E0000 Area 0 (128 kbytes) Area 1 (128 kbytes) Area 2 (128 kbytes) Area 3 (128 kbytes) Area 4 (128 kbytes) Area 5 (128 kbytes) Area 6 (128 kbytes) H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'0000 H'FFFF Area 7 (15 Mbytes) H'FFFFFF H'FFFFFF (1) Advanced mode When ASS = 0 (2) Advanced mode When ASS = 1 (3) Normal mode Figure 6.2 Overview of Area Partitioning Rev.3.00 Mar. 26, 2007 Page 145 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the burst ROM interface, the number of states is one or two regardless of the ASTCR setting. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Rev.3.00 Mar. 26, 2007 Page 146 of 772 REJ09B0355-0300 Section 6 Bus Controller Table 6.3 shows the bus specifications for each basic bus interface area. Table 6.3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH Wn1 -- 0 WCRL Wn0 -- 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 8 2 3 0 0 1 2 3 1 0 1 -- 0 -- 0 1 1 0 1 6.3.3 Memory Interfaces The H8S/2245 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; and a burst ROM interface that allows direct connection of burst ROM. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. Rev.3.00 Mar. 26, 2007 Page 147 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface should be referred to for further details. Area 0 Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. The size of area 0 is switched between 128 kbytes and 2 Mbytes according to the state of the ASS bit. Areas 1 to 6 In external expansion mode, all of area 1 to 6 is external space. When area 1 to 3 external space is accessed, the CS1 and CS3 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. The size of areas 1 to 6 is switched between 128 kbytes and 2 Mbytes according to the state of the ASS bit. Area 7 Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. The size of area 7 is switched between 15 Mbytes and 2 Mbytes according to the state of the ASS bit. Rev.3.00 Mar. 26, 2007 Page 148 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.3.5 Areas in Normal Mode In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expansion mode the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses become external space. When external space is accessed, the CS0 signal can be output. In normal mode, the basic bus interface or burst ROM interface can be selected. Rev.3.00 Mar. 26, 2007 Page 149 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.3.6 Chip Select Signals The H8S/2245 Group can output chip select signals (CS0 to CS3) to areas 0 to 3, the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal can be output. Figure 6.3 shows an example of CSn (n = 0 to 3) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS3 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS3. In ROM-enabled expansion mode, pins CS0 to CS3 are all placed in the input state after a poweron reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS3. For details, see section 8, I/O Ports. Bus cycle T1 T2 T3 Address bus Area n external address CSn Figure 6.3 CSn Signal Output Timing (n = 0 to 3) 6.4 Basic Timing The CPU is driven by a system clock (), denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip peripheral modules, and the external address space. Rev.3.00 Mar. 26, 2007 Page 150 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.4.1 On-Chip Memory (ROM, RAM) Access Timing On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 6.4 shows the on-chip memory access cycle. Figure 6.5 shows the pin states. Bus cycle T1 Internal address bus Address Read access Internal read signal Internal data bus Read data Write access Internal write signal Internal data bus Write data Figure 6.4 On-Chip Memory Access Cycle Bus cycle T1 Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 6.5 Pin States during On-Chip Memory Access Rev.3.00 Mar. 26, 2007 Page 151 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.4.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 6.6 shows the access timing for the on-chip peripheral modules. Figure 6.7 shows the pin states. Bus cycle T1 Internal address bus Address T2 Read access Internal read signal Internal data bus Read data Write access Internal write signal Internal data bus Write data Figure 6.6 On-Chip Peripheral Module Access Cycle Bus cycle T1 T2 Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 6.7 Pin States during On-Chip Peripheral Module Access Rev.3.00 Mar. 26, 2007 Page 152 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.4.3 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6.5.4, Basic Timing. 6.5 6.5.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.5.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Rev.3.00 Mar. 26, 2007 Page 153 of 772 REJ09B0355-0300 Section 6 Bus Controller Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev.3.00 Mar. 26, 2007 Page 154 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.5.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space Note: Invalid: Input state; input value is ignored. Hi-Z: High impedance. Rev.3.00 Mar. 26, 2007 Page 155 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.5.4 Basic Timing (1) 8-Bit 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 3 Figure 6.10 Bus Timing for 8-Bit 2-State Access Space Rev.3.00 Mar. 26, 2007 Page 156 of 772 REJ09B0355-0300 Section 6 Bus Controller (2) 8-Bit 3-State Access Space Figure 6.11 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 3 High impedance Figure 6.11 Bus Timing for 8-Bit 3-State Access Space Rev.3.00 Mar. 26, 2007 Page 157 of 772 REJ09B0355-0300 Section 6 Bus Controller (3) 16-Bit 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 3 Figure 6.12 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) Rev.3.00 Mar. 26, 2007 Page 158 of 772 REJ09B0355-0300 Section 6 Bus Controller Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 3 Figure 6.13 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.3.00 Mar. 26, 2007 Page 159 of 772 REJ09B0355-0300 Section 6 Bus Controller Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 3 Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.3.00 Mar. 26, 2007 Page 160 of 772 REJ09B0355-0300 Section 6 Bus Controller (4) 16-Bit 3-State Access Space Figures 6.15 to 6.17 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the odd address, and the lower half (D7 to D0) for the even address. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 3 High impedance Figure 6.15 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) Rev.3.00 Mar. 26, 2007 Page 161 of 772 REJ09B0355-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 3 Valid Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.3.00 Mar. 26, 2007 Page 162 of 772 REJ09B0355-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 3 Valid Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.3.00 Mar. 26, 2007 Page 163 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.5.5 Wait Control When accessing external space, the H8S/2245 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. (2) Pin Wait Insertion Using WAIT Pin Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Rev.3.00 Mar. 26, 2007 Page 164 of 772 REJ09B0355-0300 Section 6 Bus Controller Figure 6.18 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6.18 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. Rev.3.00 Mar. 26, 2007 Page 165 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.6 6.6.1 Burst ROM Interface Overview With the H8S/2245 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.6.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6.19 (a) and (b). The timing shown in figure 6.19 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.19 (b) is for the case where both these bits are cleared to 0. Rev.3.00 Mar. 26, 2007 Page 166 of 772 REJ09B0355-0300 Section 6 Bus Controller Full access T1 T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.19 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev.3.00 Mar. 26, 2007 Page 167 of 772 REJ09B0355-0300 Section 6 Bus Controller Full access T1 T2 Burst access T1 T1 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.19 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.6.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.5.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev.3.00 Mar. 26, 2007 Page 168 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.7 6.7.1 Idle Cycle Operation When the H8S/2245 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6.20 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Address bus CS (area A) CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6.20 Example of Idle Cycle Operation (1) Rev.3.00 Mar. 26, 2007 Page 169 of 772 REJ09B0355-0300 Section 6 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal mode. Figure 6.21 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Address bus CS (area A) CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS0 = 1) T1 T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD HWR Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS0 = 0) Figure 6.21 Example of Idle Cycle Operation (2) Rev.3.00 Mar. 26, 2007 Page 170 of 772 REJ09B0355-0300 Section 6 Bus Controller (3) Relationship between Chip Select (CS Signal and Read (RD Signal CS) RD) CS RD Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.22. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A Address bus CS (area A) CS (area B) RD T1 T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6.22 Relationship between Chip Select (CS and Read (RD CS) RD) CS RD Rev.3.00 Mar. 26, 2007 Page 171 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.7.2 Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High High High High High 6.8 6.8.1 Bus Release Overview The H8S/2245 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, it can issue a bus request off-chip. 6.8.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2245 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Rev.3.00 Mar. 26, 2007 Page 172 of 772 REJ09B0355-0300 Section 6 Bus Controller If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. In the event of simultaneous external bus release request, and external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 6.8.3 Pin States in External Bus Released State Table 6.6 shows pin states in the external bus released state. Table 6.6 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance Rev.3.00 Mar. 26, 2007 Page 173 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.8.4 Transition Timing Figure 6.23 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 T1 T2 External bus released state High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. Figure 6.23 Bus-Released State Transition Timing Rev.3.00 Mar. 26, 2007 Page 174 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.8.5 Usage Note When MSTPCR has been set to H'FFFF or H'EFFF and a transition has been made to sleep mode, the external bus release function is stopped. If the external bus release function is to be used in sleep mode, H'FFFF or H'EFFF should not be set in MSTPCR. 6.9 6.9.1 Bus Arbitration Overview The H8S/2245 Group has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.9.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev.3.00 Mar. 26, 2007 Page 175 of 772 REJ09B0355-0300 Section 6 Bus Controller 6.9.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. * If the CPU is in sleep mode, it transfers the bus immediately. DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 6.9.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The RD signal remains low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD signal may change from the low level to the high-impedance state. 6.10 Resets and the Bus Controller In a power-on reset, the H8S/2245, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller's registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored and write data is not guaranteed. Rev.3.00 Mar. 26, 2007 Page 176 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Section 7 Data Transfer Controller 7.1 Overview The H8S/2245 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features * Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev.3.00 Mar. 26, 2007 Page 177 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit SYSCR must be set to 1. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR DTC service request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register Figure 7.1 Block Diagram of DTC Rev.3.00 Mar. 26, 2007 Page 178 of 772 REJ09B0355-0300 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTVECR DTCERA to DTCERF Section 7 Data Transfer Controller 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W --* --* --* --* --* --* 2 2 2 2 2 2 Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF Address* --* --* --* --* --* --* 3 3 3 3 3 3 1 R/W R/W R/W H'FF30 to H'FF35 H'FF37 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev.3.00 Mar. 26, 2007 Page 179 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2 7.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 Undefined -- 6 SM0 Undefined -- 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined -- Initial value : R/W : MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Rev.3.00 Mar. 26, 2007 Page 180 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode -- Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer Rev.3.00 Mar. 26, 2007 Page 181 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- Undefined -- Initial value : R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0--Reserved: These bits have no effect on DTC operation, and should always be written with 0 in a write. Rev.3.00 Mar. 26, 2007 Page 182 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev.3.00 Mar. 26, 2007 Page 183 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- R/W : CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size while CRAL functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 7.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- R/W : CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev.3.00 Mar. 26, 2007 Page 184 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value : R/W : The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] 1. When DISEL = 1 and data transfer ends 2. When the specified number of transfers end 1 DTC activation by this interrupt is enabled [Holding condition] When DISEL = 0 and the specified number of transfers have not ended Note: n = 7 to 0 (Initial value) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.3, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. Rev.3.00 Mar. 26, 2007 Page 185 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2.8 Bit DTC Vector Register (DTVECR) : 7 0 6 5 0 4 3 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : 0 *1 R/(W)*2 R/(W) 0 0 0 0 0 *2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W) Notes: 1. A value of 1 can only be written to the SWDTE bit. 2. DTVEC6 to DTVEC0 bits can only be written when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] 1. When DISEL = 0 and the specified number of transfers have not ended 2. When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. 1 DTC software activation is enabled [Holding conditions] 1. When DISEL = 1 and data transfer ends 2. When the specified number of transfers end 3. During data transfer due to software activation (Initial value) Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. Rev.3.00 Mar. 26, 2007 Page 186 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. For details, see section 18.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 14--Module Stop (MSTP14): Specifies the DTC module stop mode. Bit 14 MSTP14 0 1 Description DTC module stop mode cleared DTC module stop mode set (Initial value) 7.3 7.3.1 Operation Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Rev.3.00 Mar. 26, 2007 Page 187 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Figure 7.2 shows a flowchart of DTC operation. Start Read DTC vector Read register information Next transfer Data transfer Write register information CHNE = 1? No Transfer counter = 0 or DISEL = 1? No Clear an activation flag Yes Yes Clear DTCER End * Interrupt exception handling Note: * For details on interrupt handling, see the sections dealing with the individual peripheral modules. Figure 7.2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Rev.3.00 Mar. 26, 2007 Page 188 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Table 7.2 outlines the functions of the DTC. Table 7.2 DTC Functions Address Registers Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible * Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues * Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Activation Source * * * * * * IRQ TPU TGI 8-bit timer CMI SCI TXI or RXI A/D converter ADI Software Transfer Transfer Source Destination 24 bits 24 bits 7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 7.3 shows activation source and Rev.3.00 Mar. 26, 2007 Page 189 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. As there are a number of activation sources, the activation source flag is not cleared with the last byte (or word) transfer. Take appropriate measures at each interrupt. Table 7.3 Activation Source and DTCER Clearance When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended The SWDTE bit remains set to 1 An interrupt request is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt When the DISEL Bit Is 0 and the Specified Number of Activation Source Transfers Have Not Ended Software activation The SWDTE bit is cleared to 0 Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Selection circuit DTC DTVECR Interrupt controller Interrupt mask CPU Figure 7.3 Block Diagram of DTC Activation Source Control Rev.3.00 Mar. 26, 2007 Page 190 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. 7.3.3 DTC Vector Table Figure 7.4 shows the correspondence between DTC vector addresses and register information. Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Rev.3.00 Mar. 26, 2007 Page 191 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400 + DTVECR [6:0] << 1 H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A Interrupt Source Write to DTVECR DTCE* -- Priority High IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ADI (A/D conversion end) TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C (GR0C compare match/ input capture) TGI0D (GR0D compare match/ input capture) TGI1A (GR1A compare match/ input capture) TGI1B (GR1B compare match/ input capture) TGI2A (GR2A compare match/ input capture) TGI2B (GR2B compare match/ input capture) External pin 16 17 18 19 20 21 22 23 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 Low A/D TPU channel 0 28 32 33 34 35 TPU channel 1 40 41 TPU channel 2 44 45 Rev.3.00 Mar. 26, 2007 Page 192 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Origin of Interrupt Source 8-bit timer channel 0 8-bit timer channel 1 SCI channel 0 SCI channel 1 SCI channel 2 Interrupt Source CMIA0 CMIB0 CMIA1 CMIB1 RXI0 (reception complete 0) TXI0 (transmit data empty 0) RXI1 (reception complete 1) TXI1 (transmit data empty 1) RXI2 (reception complete 2) TXI2 (transmit data empty 2) Note: * Vector Number 64 65 68 69 81 82 85 86 89 90 Vector Address H'0480 H'0482 H'0488 H'048A H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 DTCE* DTCED3 DTCED2 DTCED1 DTCED0 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 Priority High Low DTCE bits with no corresponding interrupt are reserved, and should be written with 0. DTC vector address Register information start address Register information Next transfer Figure 7.4 Correspondence between DTC Vector Address and Register Information Rev.3.00 Mar. 26, 2007 Page 193 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF). Lower address Register information start address 0 MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 Chain transfer Figure 7.5 Location of DTC Register Information in Address Space Rev.3.00 Mar. 26, 2007 Page 194 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. Table 7.5 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 7.6 Memory Mapping in Normal Mode Rev.3.00 Mar. 26, 2007 Page 195 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial states of the transfer counter and the address register specified as the repeat area are restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in repeat mode. Table 7.6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used SAR or DAR Transfer DAR or SAR Figure 7.7 Memory Mapping in Repeat Mode Rev.3.00 Mar. 26, 2007 Page 196 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. A block area is specified for either the transfer source or the transfer destination. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory mapping in block transfer mode. Table 7.7 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Block size count Transfer count Rev.3.00 Mar. 26, 2007 Page 197 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller First block SAR or DAR * * * Block area Transfer DAR or SAR nth block Figure 7.8 Memory Mapping in Block Transfer Mode Rev.3.00 Mar. 26, 2007 Page 198 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows the memory map for chain transfer. When activated, the DTC reads the register information start address stored at the vector address, which corresponds to the activation request, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 7.9 Chain Transfer Memory Map Rev.3.00 Mar. 26, 2007 Page 199 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 7.3.9 Operation Timing Figures 7.10, 7.11, and 7.12 show examples of DTC operation timings. DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Transfer information write Figure 7.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) DTC activation request DTC request Vector read Address Transfer information read Data transfer Read Write Read Write Transfer information write Figure 7.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) Rev.3.00 Mar. 26, 2007 Page 200 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Read Write Data transfer Transfer Transfer information information write read Transfer information write Figure 7.12 DTC Operation Timing (Example of Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution statuses for a single DTC data transfer, and table 7.9 shows the number of states required for each execution status. Table 7.8 DTC Execution Statuses Vector Read I 1 1 Register Information Read/Write J 6 6 6 Data Read K 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer 1 Legend: N: Block size (initial setting of CRAH and CRAL) Rev.3.00 Mar. 26, 2007 Page 201 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller Table 7.9 Number of States Required for Each Execution Status OnChip RAM 32 1 SI SJ -- 1 OnChip ROM 16 1 1 -- OnChip I/O Registers 8 2 -- -- 16 2 -- -- 2 4 -- External Devices 8 3 6+2m -- 2 2 -- 16 3 3+m -- Object to be Accessed Bus width Access states Execution Vector read status Register information read/write Byte data read Word data read Byte data write Word data write Internal operation SK SK SL SL SM 1 1 1 1 1 1 1 1 2 4 2 4 2 2 2 2 1 2 4 2 4 3+m 6+2m 3+m 6+2m 2 2 2 2 3+m 3+m 3+m 3+m m: Number of wait states in external device access The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. Rev.3.00 Mar. 26, 2007 Page 202 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.11 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev.3.00 Mar. 26, 2007 Page 203 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.3.12 Examples of Use of the DTC (1) Normal Mode The first example shows how the DTC can be used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC, and then DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. Rev.3.00 Mar. 26, 2007 Page 204 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller (2) Software Activation The second example shows how the DTC can be used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev.3.00 Mar. 26, 2007 Page 205 of 772 REJ09B0355-0300 Section 7 Data Transfer Controller 7.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTE ND) is generated. When one data transfer ends, or the specified number of data transfers end, with the DISEL bit set to 1, after the end of the data transfer the SWDTE bit remains set to 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.5 Usage Notes Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. See section 18, Power-Down Modes, for details. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. Rev.3.00 Mar. 26, 2007 Page 206 of 772 REJ09B0355-0300 Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview The H8S/2245 Group has 11 I/O ports (ports 1, 2, 3, 5, and A to G), and one input-only port (port 4). Table 8.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E have a built-in MOS input pull-up function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1 and A to F can drive a single TTL load and 90-pF capacitive load, and ports 2, 3, 5, and G can drive a single TTL load and 30-pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, and A to C can drive an LED (10-mA sink current). Port 2 and the interrupt input pins (IRQ0 to IRQ7) are Schmitt-triggered inputs. Rev.3.00 Mar. 26, 2007 Page 207 of 772 REJ09B0355-0300 Port P17/TIOCB2/TCLKD P16/TIOCA2 P15/TIOCB1/TCLKC P14/TIOCA1 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 When DDR=0: Input port also functioning as TPU I/O pins (TCLKA, TCLKB, TIOCA0, TIOCB0, TIOCC0, TIOCD0) When DDR= 1: Address output Description 8-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) Pins 1 1 Mode 1 Mode 2* Mode 3* Mode 4 1 1 Mode 5 Mode 6* Mode 7* Table 8.1 Section 8 I/O Ports Port 1 * 8-bit I/O port Port Functions Rev.3.00 Mar. 26, 2007 Page 208 of 772 REJ09B0355-0300 P27/TMO1 P26/TMO0 P25/TMCI1 P24/TMRI1 P23/TMCI0 P22/TMRI0 P21 P20 P35/SCK1/IRQ5 P34/SCK0/IRQ4 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 P43/AN3 P42/AN2 P41/AN1 P40/AN0 P53 P52/SCK2 P51/RxD2 P50/TxD2 8-bit I/O port also functioning as 8-bit timer (channels 0 and 1) I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1) 6-bit I/O port also functioning as SCI (channels 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) and interrupt input pins (IRQ5, IRQ4) 4-bit input port also functioning as A/D converter analog inputs (AN3 to AN0) 4-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) Port 2 * 8-bit I/O port * Schmitttriggered input Port 3 * 6-bit I/O port * Open-drain output capability * Schmitttriggered input (IRQ5, IRQ4) Port 4 * 4-bit input port Port 5 * 4-bit I/O port Port PA3/A19 to PA0/A16 I/O port Address output When DDR = 0 (after reset): input ports When DDR = 1: address output When DDR = 0 (after reset): input port When DDR = 1: address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O port Description Pins Mode 1 1 Mode 2* 1 Mode 3* Mode 4 Mode 5 1 Mode 6* 1 Mode 7* Port A * 4-bit I/O port * Built-in MOS input pull-up * Open-drain output capability Port B * 8-bit I/O port * Built-in MOS input pull-up PB7/A15 to PB0/A8 Address output When DDR = 0 (after reset): input port When DDR = 1: address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O port Address output I/O port Address output I/O port Port C * 8-bit I/O port * Built-in MOS input pull-up PC7/A7 to PC0/A0 Address output I/O port Section 8 I/O Ports Rev.3.00 Mar. 26, 2007 Page 209 of 772 REJ09B0355-0300 Port PD7/D15 to PD0/D8 Data bus input/output I/O port Data bus input/output I/O port Description Pins Mode 1 1 Mode 2* 1 Mode 3* Mode 4 Mode 5 1 Mode 6* Mode 7* 1 Port D * 8-bit I/O port * Built-in MOS input pull-up PE7/D7 to PE0/D0 In 8-bit bus mode: I/O port I/O port In 16-bit bus mode: data bus input/output When DDR = 0: input port When DDR = 1 (after reset): output When DDR = 0 (after reset): input port When DDR = 1: output I/O port When DDR = 0: input port When DDR = 1 (after reset): o output In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/ output Section 8 I/O Ports Port E * 8-bit I/O port * Built-in MOS input pull-up PF7/ I/O port Rev.3.00 Mar. 26, 2007 Page 210 of 772 REJ09B0355-0300 When DDR = 0 (after reset): input port When DDR = 1: output I/O port PF6/AS PF5/RD PF4/HWR PF3/LWR/ IRQ3 I/O port also functioning as interrupt input pins (IRQ3 to IRQ0) AS, RD, HWR, LWR output AS, RD, HWR, LWR output I/O port also functioning as interrupt input pins (IRQ3 to IRQ0) Port F * 8-bit I/O port * Schmitttriggered input (IRQ3 to IRQ0) Port PF2/ WAIT/ BREQO/ IRQ2 When WAITE = 1 and BREQOE = 0: WAIT input also functioning as interrupt input pin (IRQ2) When WAITE = 0 and BREQOE = 1: BREQO output also functioning as interrupt input pin (IRQ2) PF1/ BACK/ IRQ1 PF0/ BREQ/ IRQ0 When BRLE = 0 (after reset): I/O port also functioning as interrupt input pins (IRQ1, IRQ0) When BRLE = 1: BREQ input, BACK output also functioning as interrupt input pins (IRQ1, IRQ0) When WAITE = 0 and BREQOE = 1: BREQO output also functioning as interrupt input pin (IRQ2) When BRLE = 0 (after reset): I/O port also functioning as interrupt input pins (IRQ1, IRQ0) When BRLE = 1: BREQ input, BACK output also functioning as interrupt input pins (IRQ1, IRQ0) I/O port also functioning as interrupt input pins (IRQ3 to IRQ0) When WAITE = 1 and BREQOE = 0: WAIT input also functioning as interrupt input pin (IRQ2) When WAITE = 0 and BREQOE = 0 (after reset): I/O port also functioning as interrupt input pin (IRQ2) When WAITE = 0 and BREQOE = 0 (after reset): I/O port also functioning as interrupt input pin (IRQ2) Description Pins Mode 1 Mode 2* Mode 4 Mode 5 I/O port also functioning as interrupt input pin (IRQ3 to IRQ0) 1 Mode 3* 1 Mode 6* 1 Mode 7* 1 Port F * 8-bit I/O port * Schmitttriggered input (IRQ3 to IRQ0) Section 8 I/O Ports Rev.3.00 Mar. 26, 2007 Page 211 of 772 REJ09B0355-0300 Port When DDR = 0 : input port 3 When DDR = 1* : CS0 output I/O port also functioning as interrupt input pins (IRQ6, IRQ7) and A/D converter input pin (ADTRG) I/O port also functioning as interrupt input pins (IRQ7, IRQ6) and A/D converter input pin (ADTRG) When DDR = 0 (after reset): input port also functioning as interrupt input pin (IRQ7) When DDR = 1: CS1, CS2, CS3 output also functioning as interrupt input pin (IRQ7) I/O port also functioning as interrupt input pin (IRQ6) and A/D converter input pin (ADTRG) When DDR = 0 : input port 3 When DDR = 1* : CS0 output *2 *2 I/O port also functioning as interrupt input pins (IRQ7, IRQ6) and A/D converter input pin (ADTRG) Section 8 I/O Ports Description Pins Mode 1 1 Mode 2* 1 Mode 3* Mode 4 Mode 5 1 Mode 6* 1 Mode 7* Port G * 5-bit I/O PG4/CS0 port * Schmitttriggered input (IRQ7, IRQ6) PG3/CS1 PG2/CS2 PG1/CS3/ IRQ7 Rev.3.00 Mar. 26, 2007 Page 212 of 772 REJ09B0355-0300 PG0/IRQ6/ ADTRG Notes: 1. Cannot be used in the H8S/2240. 2. After a reset in mode 2 or 6. 3. After a reset in mode 1, 4 or 5. Section 8 I/O Ports 8.2 8.2.1 Port 1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and an address bus output function. Port 1 pin functions change according to the operating mode. Figure 8.1 shows the port 1 pin configuration. Port 1 pins P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input) Port 1 P14 (I/O)/TIOCA1 (I/O) P13 (I/O)/TIOCD0 (I/O)/TCLKB (input)/A23 (output) P12 (I/O)/TIOCC0 (I/O)/TCLKA (input)/A22 (output) P11 (I/O)/TIOCB0 (I/O)/A21 (output) P10 (I/O)/TIOCA0 (I/O)/A20 (output) Pin functions in modes 4 to 6* P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input) P14 (I/O)/TIOCA1 (I/O) P13 (input)/TIOCD0 (I/O)/TCLKB (input)/A23 (output) P12 (input)/TIOCC0 (I/O)/TCLKA (input)/A22 (output) P11 (input)/TIOCB0 (I/O)/A21 (output) P10 (input)/TIOCA0 (I/O)/A20 (output) Pin functions in modes 1 to 3 and 7* P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input) P14 (I/O)/TIOCA1 (I/O) P13 (I/O)/TIOCD0 (I/O)/TCLKB (input) P12 (I/O)/TIOCC0 (I/O)/TCLKA (input) P11 (I/O)/TIOCB0 (I/O) P10 (I/O)/TIOCA0 (I/O) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.1 Port 1 Pin Functions Rev.3.00 Mar. 26, 2007 Page 213 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.2.2 Register Configuration Table 8.2 shows the port 1 register configuration. Table 8.2 Name Port 1 data direction register Port 1 data register Port 1 register Note: * Port 1 Registers Abbreviation P1DDR P1DR PORT1 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB0 H'FF60 H'FF50 Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the TPU is initialized by a manual reset, the pin states are determined by the P1DDR and P1DR specifications. Whether the address output pins maintain their output state or go to the high-impedance state in a transition to software standby mode is selected by the OPE bit in SBYCR. * Modes 1 to 3 and 7 The corresponding port 1 pins are output ports when P1DDR is set to 1, and input ports when cleared to 0. Note: Modes 2, 3, and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 214 of 772 REJ09B0355-0300 Section 8 I/O Ports * Modes 4 to 6 The corresponding port 1 pins are address outputs when P13DDR to P10DDR are set to 1, and input ports when cleared to 0. The corresponding port 1 pins are output ports when P17DDR to P14DDR are set to 1, and input ports when cleared to 0. Note: Mode 6 cannot be used in the H8S/2240. Port 1 Data Register (P1DR) Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port 1 Register (PORT1) Bit : 7 P17 Initial value : R/W : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 215 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.2.3 Pin Functions Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and address output pins (A23 to A20). Port 1 pin functions are shown in table 8.3. Table 8.3 Pin P17 /TIOCB2/ TCLKD Port 1 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR2 to CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0, and bit P17DDR. TPU Channel 2 Setting Table Below (1) Table Below (2) P17DDR Pin function -- TIOCB2 output 0 P17 input 2 1 P17 output 1 TIOCB2 input* TCLKD input* Notes: 1. TIOCB2 input when input capture is set (IOB3 to IOB0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). 2. TCLKD input when the TCR0 setting is: TPSC2 to TPSC0 = B'111. TCLKD input when channel 2 is set to phase counting mode (MD3 to MD0 = B'01xx). TPU Channel 2 Setting MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0000, B'01xx B'0010 B'0000 B'0001 to -- B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Output compare output -- -- Other than B'010 PWM mode 2 output B'010 -- Legend: x: Don't care Rev.3.00 Mar. 26, 2007 Page 216 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P16/TIOCA2 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR2 to CCLR0 in TCR2), and bit P16DDR. TPU Channel 2 Setting P16DDR Pin function Note: Table Below (1) -- TIOCA2 output Table Below (2) 0 P16 input 1 P16 output 1 TIOCA2 input* 1. TIOCA2 input when input capture is set (IOA3 to IOA0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). TPU Channel 2 Setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx B'0000 B'0001 to B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- (2) B'001x B'xx00 (1) B'0010 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- -- Output compare output -- PWM mode 1 2 output* Other than B'001 PWM mode 2 output B'001 -- Legend: x: Don't care Note: 2. TIOCB2 output is disabled. Rev.3.00 Mar. 26, 2007 Page 217 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P15/TIOCB1/ TCLKC Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR2 to CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0 and TCR2, and bit P15DDR. TPU Channel 1 Setting P15DDR Pin function Table Below (1) -- TIOCB1 output Table Below (2) 0 P15 input TCLKC input* 2 1 P15 output 1 TIOCB1 input* Notes: 1. TIOCB1 input when input capture is set (IOB3 to IOB0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). 2. TCLKC input when either the TCR0 or TCR2 setting is: TPSC2 to TPSC0 = B'110. TCLKC input when channel 2 is set to phase counting mode (MD3 to MD0 = B'01xx). TPU Channel 1 Setting MD3 to MD0 IOB3 to IOB0 (2) (1) (2) (2) B'xx00 (1) (2) B'0000, B'01xx B'0010 B'0000 B'0001 to -- B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- -- B'0011 Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Output compare output -- -- Other than B'010 PWM mode 2 output B'010 -- Legend: x: Don't care Rev.3.00 Mar. 26, 2007 Page 218 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P14/TIOCA1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR2 to CCLR0 in TCR1), and bit P14DDR. TPU Channel 1 Setting P14DDR Pin function Note: Table Below (1) -- TIOCA1 output Table Below (2) 0 P14 input 1 P14 output 1 TIOCA1 input* 1. TIOCA1 input when input capture is set (IOA3 to IOA0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). TPU Channel 1 Setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx B'0000 B'0001 to B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- (2) B'001x B'xx00 (1) B'0010 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- -- Output compare output -- PWM mode 1 2 output* Other than B'001 PWM mode 2 output B'001 -- Legend: x: Don't care Note: 2. TIOCB1 output is disabled. Rev.3.00 Mar. 26, 2007 Page 219 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P13/TIOCD0/ TCLKB/A23 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, and bit P13DDR. Operating Mode TPU Channel 0 Setting P13DDR Pin function Modes 1, 2, 3, 7* Table Below (1) -- TIOCD0 output 1 Modes 4, 5, 6* Table Below (1) 0 1 1 Table Below (2) 0 1 Table Below (2) 0 P13 input 1 A23 output P13 TIOCD0 A23 P13 input output output output TIOCD0 2 input* TCLKB input* 3 TIOCD0 2 input* Notes: 1. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. 2. TIOCD0 input when input capture is set (IOD3 to IOD0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). 3. TCLKB input when the TCR0, TCR1, or TCR2 setting is: TPSC2 to TPSC0 = B'101. TCLKB input when channel 1 is set to phase counting mode (MD3 to MD0 = B'01xx). TPU Channel 0 Setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'110 PWM mode 2 output B'110 -- Output compare output -- -- -- Legend: x: Don't care Rev.3.00 Mar. 26, 2007 Page 220 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P12/TIOCC0/ TCLKA/A22 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, and bit P12DDR. Operating Mode TPU Channel 0 Setting P12DDR Pin function Modes 1, 2, 3, 7* Table Below (1) -- TIOCC0 output 1 Modes 4, 5, 6* Table Below (1) 0 1 1 Table Below (2) 0 1 Table Below (2) 0 P12 input 1 A22 output P12 TIOCC0 A22 P12 input output output output TIOCC0 2 input* TCLKA input* 3 TIOCC0 2 input* Notes: 1. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. 2. TIOCC0 input when input capture is set (IOC3 to IOC0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). 3. TCLKA input when the TCR0, TCR1, or TCR2 setting is: TPSC2 to TPSC0 = B'100. TCLKA input when channel 1 is set to phase counting mode (MD3 to MD0 = B'01xx). TPU Channel 0 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'001x B'xx00 (1) B'0010 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'101 PWM mode 2 output B'101 -- Output compare output -- PWM mode 1 4 output* -- Legend: x: Don't care Note: 4. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies. Rev.3.00 Mar. 26, 2007 Page 221 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P11/TIOCB0/ A21 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), and bit P11DDR. Operating Mode TPU Channel 0 Setting P11DDR Pin function Modes 1, 2, 3, 7* Table Below (1) -- TIOCB0 output 1 Modes 4, 5, 6* Table Below (1) 0 1 1 Table Below (2) 0 1 Table Below (2) 0 P11 input 1 A21 output P11 TIOCB0 A21 P11 input output output output TIOCB0 2 input* TIOCB0 2 input* Notes: 1. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. 2. TIOCB0 input when input capture is set (IOB3 to IOB0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). TPU Channel 0 Setting MD3 to MD0 IOB3 to IOB0 (1) B'0000 B'0000 B'0001 to B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- (2) (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- -- Output compare output -- -- Other than B'010 PWM mode 2 output B'010 -- Legend: x: Don't care Rev.3.00 Mar. 26, 2007 Page 222 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P10/TIOCA0/ A20 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), and bit P10DDR. Operating Mode TPU Channel 0 Setting P10DDR Pin function Modes 1, 2, 3, 7* Table Below (1) -- TIOCA0 output 1 Modes 4, 5, 6* Table Below (1) 0 1 1 Table Below (2) 0 1 Table Below (2) 0 P10 input 1 A20 output P10 TIOCA0 A20 P10 input output output output TIOCA0 2 input* TIOCA0 2 input* Notes: 1. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. 2. TIOCA0 input when input capture is set (IOA3 to IOA0 = B'10xx) in normal operating mode (MD3 to MD0 = B'0000). TPU Channel 0 Setting MD3 to MD0 IOA3 to IOA0 (1) B'0000 B'0000 B'0001 to B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- (2) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- -- Output compare output -- PWM mode 1 3 output* Other than B'001 PWM mode 2 output B'001 -- Legend: x: Don't care Note: 3. TIOCB0 output is disabled. Rev.3.00 Mar. 26, 2007 Page 223 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.3 8.3.1 Port 2 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 8.2 shows the port 2 pin configuration. Port 2 pins P27 (I/O)/ TMO1 (output) P26 (I/O)/ TMO0 (output) P25 (I/O)/ TMCI1 (input) Port 2 P24 (I/O)/ TMRI1 (input) P23 (I/O)/ TMCI0 (input) P22 (I/O)/ TMRI0 (input) P21 (I/O) P20 (I/O) Figure 8.2 Port 2 Pin Functions 8.3.2 Register Configuration Table 8.4 shows the port 2 register configuration. Table 8.4 Name Port 2 data direction register Port 2 data register Port 2 register Note: * Port 2 Registers Abbreviation P2DDR P2DR PORT2 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB1 H'FF61 H'FF51 Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 224 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 2 Data Direction Register (P2DDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : R/W : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the 8-bit timer is initialized by a manual reset, the pin states are determined by the P2DDR and P2DR specifications. Port 2 Data Register (P2DR) Bit : 7 P27DR Initial value : R/W : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 225 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 2 Register (PORT2) Bit : 7 P27 Initial value : R/W : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R 3 P23 --* R 2 P22 --* R 1 P21 --* R 0 P20 --* R Note: * Determined by state of pins P27 to P20. PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 226 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.3.3 Pin Functions Port 2 pins also function as 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 8.5. Table 8.5 Pin P27/TMO1 Port 2 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the bits OS3 to OS0 in TCSR1 of the 8-bit timer, and bit P27DDR. OS3 to OS0 P27DDR Pin function 0 P27 input All 0 1 P27 output Any 1 -- TMO1 output P26/TMO0 The pin function is switched as shown below according to the combination of bits OS3 to OS0 in TCSR0, and bit P26DDR. OS3 to OS0 P26DDR Pin function 0 P26 input All 0 1 P26 output Any 1 -- TMO0 output P25/TMCI1 This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of bit P25DDR. P25DDR Pin function 0 P25 input TMCI1 input 1 P25 output Rev.3.00 Mar. 26, 2007 Page 227 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P24/TMRI1 Selection Method and Pin Functions This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of bit P24DDR. P24DDR Pin function 0 P24 input TMRI1 input 1 P24 output P23/TMCI0 This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of bit P23DDR. P23DDR Pin function 0 P23 input TMCI0 input 1 P23 output P22/TMRI0 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of bit P22DDR. P22DDR Pin function 0 P22 input TMRI0 input 1 P22 output P21 The pin function is switched as shown below according to the combination of bit P21DDR. P21DDR Pin function 0 P21 input 1 P21 output P20 The pin function is switched as shown below according to the combination of bit P20DDR. P20DDR Pin function 0 P20 input 1 P20 output Rev.3.00 Mar. 26, 2007 Page 228 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.4 8.4.1 Port 3 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are the same in all operating modes. The interrupt input pins (IRQ4, IRQ5) are Schmitt-triggered inputs. Figure 8.3 shows the port 3 pin configuration. Port 3 pins P35 (I/O)/ SCK1(I/O)/ IRQ5 (input) P34 (I/O)/ SCK0(I/O)/ IRQ4 (input) Port 3 P33 (I/O)/ RxD1 (input) P32 (I/O)/ RxD0 (input) P31 (I/O)/ TxD1 (output) P30 (I/O)/ TxD0 (output) Figure 8.3 Port 3 Pin Functions 8.4.2 Register Configuration Table 8.6 shows the port 3 register configuration. Table 8.6 Name Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register Port 3 Registers Abbreviation P3DDR P3DR PORT3 P3ODR R/W W R/W R R/W Initial Value* H'00 H'00 Undefined H'00 1 Address* H'FEB2 H'FF62 H'FF52 H'FF76 2 Notes: 1. Value of bits 5 to 0. 2. Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 229 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 3 Data Direction Register (P3DDR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read. P3DDR cannot be modified. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized by a reset and in standby mode, the pin states are determined by the P3DDR and P3DR specifications. Port 3 Data Register (P3DR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W Undefined Undefined P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 230 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 3 Register (PORT3) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 P35 --* R 4 P34 --* R 3 P33 --* R 2 P32 --* R 1 P31 --* R 0 P30 --* R Undefined Undefined Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after a manual reset, and in software standby mode. Port 3 Open Drain Control Register (P3ODR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Undefined Undefined P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 231 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.4.3 Pin Functions Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are shown in table 8.7. Table 8.7 Pin P35/SCK1/IRQ5 Port 3 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR. CKE1 C/A CKE0 P35DDR Pin function 0 P35 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK1 input pin SCK1 SCK1 P35 1 1 1 output pin* output pin* output pin* IRQ5 interrupt input pin* 2 Notes: 1. When P35ODR = 1, the pin becomes on NMOS open-drain output. 2. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. P34/SCK0/IRQ4 The pin function is switched as shown below according to the combination of bit C/A in the SCI0 SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 C/A CKE0 P34DDR Pin function 0 P34 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK0 input pin P34 SCK0 SCK0 1 1 1 output pin* output pin* output pin* IRQ4 interrupt input pin* 2 Notes: 1. When P34ODR = 1, the pin becomes an NMOS open-drain output. 2. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. Rev.3.00 Mar. 26, 2007 Page 232 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin P33/RxD1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE P33DDR Pin function Note: P32/RxD0 * 0 P33 input pin 0 1 P33 output pin* 1 -- RxD1 input pin When P33ODR = 1, the pin becomes an NMOS open drain output. The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR. RE P32DDR Pin function Note: * 0 P32 input pin 0 1 P32 output pin* 1 -- RxD0 input pin When P32ODR = 1, the pin becomes an NMOS open drain output. P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in the SCI1 SCR, and bit P31DDR. TE P31DDR Pin function Note: * 0 P31 input pin 0 1 P31 output pin* 1 -- TxD1 output pin* When P31ODR = 1, the pin becomes an NMOS open drain output. P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in the SCI0 SCR, and bit P30DDR. TE P30DDR Pin function Note: * 0 P30 input pin 0 1 P30 output pin* 1 -- TxD0 output pin* When P30ODR = 1, the pin becomes an NMOS open drain output. Rev.3.00 Mar. 26, 2007 Page 233 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.5 8.5.1 Port 4 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN3). Port 4 pin functions are the same in all operating modes. Figure 8.4 shows the port 4 pin configuration. Port 4 pins P43 (input)/AN3 (input) Port 4 P42 (input)/AN2 (input) P41 (input)/AN1 (input) P40 (input)/AN0 (input) Figure 8.4 Port 4 Pin Functions 8.5.2 Register Configuration Table 8.8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 8.8 Name Port 4 register Note: * Port 4 Registers Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FF53 Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 234 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 4 Register (PORT4) Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R Initial value : Undefined Undefined Undefined Undefined Note: * Determined by state of pins P43 to P40. PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bits 7 to 4 are reserved; they return an undetermined value if read. 8.5.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN3). Rev.3.00 Mar. 26, 2007 Page 235 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.6 8.6.1 Port 5 Overview Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2). Port 5 pin functions are the same in all operating modes. Figure 8.5 shows the port 5 pin configuration. Port 5 pins P53 (I/O) Port 5 P52 (I/O)/ SCK2(I/O) P51 (I/O)/ RxD2 (input) P50 (I/O)/ TxD2 (output) Figure 8.5 Port 5 Pin Functions 8.6.2 Register Configuration Table 8.9 shows the port 5 register configuration. Table 8.9 Name Port 5 data direction register Port 5 data register Port 5 register Port 5 Registers Abbreviation P5DDR P5DR PORT5 R/W W R/W R Initial Value* H'0 H'0 Undefined 1 Address* H'FEB4 H'FF64 H'FF54 2 Notes: 1. Value of bits 3 to 0. 2. Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 236 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 5 Data Direction Register (P5DDR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 W 2 0 W 1 0 W 0 0 W P53DDR P52DDR P51DDR P50DDR Undefined Undefined Undefined Undefined P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be read. P5DDR cannot be modified. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized by a reset and in standby mode, the pin states are determined by the P5DDR and P5DR specifications. Port 5 Data Register (P5DR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 P50DR 0 R/W Undefined Undefined Undefined Undefined P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P53 to P50). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 237 of 772 REJ09B0355-0300 Section 8 I/O Ports Port 5 Register (PORT5) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P53 --* R 2 P52 --* R 1 P51 --* R 0 P50 --* R Undefined Undefined Undefined Undefined Note: * Determined by state of pins P53 to P50. PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 5 pins (P53 to P50) must always be performed on P5DR. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT5 contents are determined by the pin states, as P5DDR and P5DR are initialized. PORT5 retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 238 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.6.3 Pin Functions Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2). Port 5 pin functions are shown in table 8.10. Table 8.10 Port 5 Pin Functions Pin P53 Selection Method and Pin Functions The pin function is switched as shown below according to bit P53DDR. P53DDR Pin function 0 P53 input pin 1 P53 output pin P52/SCK2 The pin function is switched as shown below according to the combination of bit C/A in the SCI2 SMR, bits CKE0 and CKE1 in SCR, and bit P52DDR. CKE1 C/A CKE0 P52DDR Pin function 0 P52 input pin 0 1 P52 output pin 0 1 -- SCK2 output pin 0 1 -- -- SCK2 output pin 1 -- -- -- SCK2 input pin P51/RxD2 The pin function is switched as shown below according to the combination of bit RE in the SCI2 SCR, and bit P51DDR. RE P51DDR Pin function 0 P51 input pin 0 1 P51 output pin 1 -- RxD2 input pin P50/TxD2 The pin function is switched as shown below according to the combination of bit TE in the SCI2 SCR, and bit P50DDR. TE P50DDR Pin function 0 P50 input pin 0 1 P50 output pin 1 -- TxD2 output pin Rev.3.00 Mar. 26, 2007 Page 239 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.7 8.7.1 Port A Overview Port A is an 4-bit I/O port. Port A pins also function as address bus outputs. The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 8.6 shows the port A pin configuration. Port A pins PA3 / A19 PA2 / A18 Port A PA1 / A17 PA0 / A16 Pin functions in modes 1, 2, 3, and 7* PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O) Pin functions in modes 4 and 5 A1 9 (output) A1 8 (output) A1 7 (output) A1 6 (output) Pin functions in mode 6* PA3 (input)/ A19 (output) PA2 (input)/ A18 (output) PA1 (input)/ A17 (output) PA0 (input)/ A16 (output) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.6 Port A Pin Functions 8.7.2 Register Configuration Table 8.11 shows the port A register configuration. Rev.3.00 Mar. 26, 2007 Page 240 of 772 REJ09B0355-0300 Section 8 I/O Ports Table 8.11 Port A Registers Name Port A data direction register Port A data register Port A register Port A MOS pull-up control register Port A open-drain control register Abbreviation PADDR PADR PORTA PAPCR PAODR R/W W R/W R R/W R/W Initial Value* H'0 H'0 Undefined H'0 H'0 1 Address* H'FEB9 H'FF69 H'FF59 H'FF70 H'FF77 2 Notes: 1. Value of bits 3 to 0. 2. Lower 16 bits of the address. Port A Data Direction Register (PADDR) Bit Initial value R/W : : : 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 0 W 2 0 W 1 0 W 0 0 W PA3DDR PA2DDR PA1DDR PA0DDR Undefined Undefined Undefined Undefined PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. Bits 7 to 4 are reserved. PADDR cannot be read; if it is, an undefined value will be read. PADDR cannot be modified. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become highimpedance when a transition is made to software standby mode. * Modes 1, 2, 3, and 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 2, 3, and 7 cannot be used in the H8S/2240. * Modes 4 and 5 The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to PA0DDR. Rev.3.00 Mar. 26, 2007 Page 241 of 772 REJ09B0355-0300 Section 8 I/O Ports * Mode 6 Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the pin an input port. Note: Mode 6 cannot be used in the H8S/2240. Port A Data Register (PADR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W Undefined Undefined Undefined Undefined PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to PA0). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. PADR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Register (PORTA) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R 0 PA0 --* R Undefined Undefined Undefined Undefined Note: * Determined by state of pins PA3 to PA0. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA3 to PA0) must always be performed on PADR. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 242 of 772 REJ09B0355-0300 Section 8 I/O Ports Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA3PCR PA2PCR PA1PCR PA0PCR Undefined Undefined Undefined Undefined PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. Bits 3 to 0 are valid in modes 1, 2, 3, 6, and 7, and all the bits are invalid in modes 4 and 5. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Open Drain Control Register (PAODR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA3ODR PA2ODR PA1ODR PA0ODR Undefined Undefined Undefined Undefined PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA3 to PA0). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. All bits are valid in modes 1, 2, 3, and 7. Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 243 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.7.3 Pin Functions Modes 1, 2, 3 and 7 In mode 1, 2, 3, and 7, port A pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 2, 3, and 7 cannot be used in the H8S/2240. Port A pin functions in modes 1, 2, 3, and 7 are shown in figure 8.7. PA3 (I/O) Port A PA2 (I/O) PA1 (I/O) PA0 (I/O) Figure 8.7 Port A Pin Functions (Modes 1, 2, 3, and 7) Modes 4 and 5 In modes 4 and 5, the lower 4 bits of port A are designated as address outputs automatically. Port A pin functions in modes 4 and 5 are shown in figure 8.8. A19 (output) Port A A18 (output) A17 (output) A16 (output) Figure 8.8 Port A Pin Functions (Modes 4 and 5) Rev.3.00 Mar. 26, 2007 Page 244 of 772 REJ09B0355-0300 Section 8 I/O Ports Mode 6 In mode 6, port A pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Note: Mode 6 cannot be used in the H8S/2240. Port A pin functions in mode 6 are shown in figure 8.9. When PADDR = 1 A19 (output) Port A A18 (output) A17 (output) A16 (output) When PADDR = 0 PA3 (input) PA2 (input) PA1 (input) PA0 (input) Figure 8.9 Port A Pin Functions (Mode 6) Rev.3.00 Mar. 26, 2007 Page 245 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.7.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2, 3, 6, and 7, and cannot be used in modes 4 and 5. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Table 8.12 summarizes the MOS input pull-up states. Table 8.12 MOS Input Pull-Up States (Port A) Modes 1 to 3, 6, 7 4, 5 PA3 to PA0 PA3 to PA0 Power-On Hardware Reset Standby Mode OFF OFF Manual Software Reset Standby Mode ON/OFF ON/OFF OFF OFF In Other Operations ON/OFF OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off. Rev.3.00 Mar. 26, 2007 Page 246 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.8 8.8.1 Port B Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 8.10 shows the port B pin configuration. Port B pins PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 Port B PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 Pin functions in modes 1, 4, and 5 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Pin functions in modes 2 and 6* PB7 (input)/A15 (output) PB6 (input)/A14 (output) PB5 (input)/A13 (output) PB4 (input)/A12 (output) PB3 (input)/A11 (output) PB2 (input)/A10 (output) PB1 (input)/A9 (output) PB0 (input)/A8 (output) Pin functions in modes 3 and 7* PB7 (I/O) PB6 (I/O) PB5 (I/O) PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.10 Port B Pin Functions Rev.3.00 Mar. 26, 2007 Page 247 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.8.2 Register Configuration Table 8.13 shows the port B register configuration. Table 8.13 Port B Registers Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Note: * Abbreviation PBDDR PBDR PORTB PBPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBA H'FF6A H'FF5A H'FF71 Lower 16 bits of the address. Port B Data Direction Register (PBDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits. * Modes 2 and 6 Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. Note: Modes 2 and 6 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 248 of 772 REJ09B0355-0300 Section 8 I/O Ports * Modes 3 and 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port B Data Register (PBDR) Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port B Register (PORTB) Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 249 of 772 REJ09B0355-0300 Section 8 I/O Ports Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When a PBDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.8.3 Pin Functions Modes 1, 4, and 5 In modes 1, 4, and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 1, 4, and 5 are shown in figure 8.11. A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Figure 8.11 Port B Pin Functions (Modes 1, 4, and 5) Rev.3.00 Mar. 26, 2007 Page 250 of 772 REJ09B0355-0300 Section 8 I/O Ports Modes 2 and 6 In modes 2 and 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. Note: Modes 2 and 6 cannot be used in the H8S/2240. Port B pin functions in modes 2 and 6 are shown in figure 8.12. When PBDDR = 1 A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When PBDDR = 0 PB7 (input) PB6 (input) PB5 (input) PB4 (input) PB3 (input) PB2 (input) PB1 (input) PB0 (input) Figure 8.12 Port B Pin Functions (Modes 2 and 6) Modes 3 and 7 In modes 3 and 7, port B pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port B pin functions in modes 3 and 7 are shown in figure 8.13. Rev.3.00 Mar. 26, 2007 Page 251 of 772 REJ09B0355-0300 Section 8 I/O Ports PB7 (I/O) PB6 (I/O) PB5 (I/O) Port B PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O) Figure 8.13 Port B Pin Functions (Modes 3 and 7) 8.8.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Table 8.14 summarizes the MOS input pull-up states. Table 8.14 MOS Input Pull-Up States (Port B) Modes 1, 4, 5 2, 3, 6, 7 Power-On Reset OFF Hardware Standby Mode OFF Manual Reset OFF ON/OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off. Rev.3.00 Mar. 26, 2007 Page 252 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.9 8.9.1 Port C Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 8.14 shows the port C pin configuration. Pin functions in modes 1, 4, and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Port C pins PC7 / A7 PC6 / A6 PC5 / A5 Port C PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Pin functions in modes 2 and 6* PC7 (input)/ A7 (output) PC6 (input)/ A6 (output) PC5 (input)/ A5 (output) PC4 (input)/ A4 (output) PC3 (input)/ A3 (output) PC2 (input)/ A2 (output) PC1 (input)/ A1 (output) PC0 (input)/ A0 (output) Pin functions in modes 3 and 7* PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.14 Port C Pin Functions Rev.3.00 Mar. 26, 2007 Page 253 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.9.2 Register Configuration Table 8.15 shows the port C register configuration. Table 8.15 Port C Registers Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Note: * Abbreviation PCDDR PCDR PORTC PCPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBB H'FF6B H'FF5B H'FF72 Lower 16 bits of the address. Port C Data Direction Register (PCDDR) Bit Initial value R/W : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits. * Modes 2 and 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Note: Modes 2 and 6 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 254 of 772 REJ09B0355-0300 Section 8 I/O Ports * Modes 3 and 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port C Data Register (PCDR) Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port C Register (PORTC) Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 255 of 772 REJ09B0355-0300 Section 8 I/O Ports Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When a PCDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.9.3 Pin Functions Modes 1, 4, and 5 In modes 1, 4, and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 1, 4, and 5 are shown in figure 8.15. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 8.15 Port C Pin Functions (Modes 1, 4, and 5) Rev.3.00 Mar. 26, 2007 Page 256 of 772 REJ09B0355-0300 Section 8 I/O Ports Modes 2 and 6 In modes 2 and 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Note: Modes 2 and 6 cannot be used in the H8S/2240. Port C pin functions in modes 2 and 6 are shown in figure 8.16. When PCDDR = 1 A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input) Figure 8.16 Port C Pin Functions (Modes 2 and 6) Modes 3 and 7 In modes 3 and 7, port C pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port C pin functions in modes 3 and 7 are shown in figure 8.17. Rev.3.00 Mar. 26, 2007 Page 257 of 772 REJ09B0355-0300 Section 8 I/O Ports PC7 (I/O) PC6 (I/O) PC5 (I/O) Port C PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Figure 8.17 Port C Pin Functions (Modes 3 and 7) 8.9.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Table 8.16 summarizes the MOS input pull-up states. Table 8.16 MOS Input Pull-Up States (Port C) Modes 1, 4, 5 2, 3, 6, 7 Power-On Reset OFF Hardware Standby Mode OFF Manual Reset OFF ON/OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off. Rev.3.00 Mar. 26, 2007 Page 258 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.10 8.10.1 Port D Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 8.18 shows the port D pin configuration. Port D pins PD7 / D15 PD6 / D14 PD5 / D13 Port D PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 Pin functions in modes 1, 2, 4, 5, and 6* D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Pin functions in modes 3 and 7* PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.18 Port D Pin Functions Rev.3.00 Mar. 26, 2007 Page 259 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.10.2 Register Configuration Table 8.17 shows the port D register configuration. Table 8.17 Port D Registers Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBC H'FF6C H'FF5C H'FF73 Lower 16 bits of the address. Port D Data Direction Register (PDDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. * Modes 1, 2, 4, 5, and 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O. Note: Modes 2 and 6 cannot be used in the H8S/2240. * Modes 3 and 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 260 of 772 REJ09B0355-0300 Section 8 I/O Ports Port D Data Register (PDDR) Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port D Register (PORTD) Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 261 of 772 REJ09B0355-0300 Section 8 I/O Ports Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.10.3 Pin Functions Modes 1, 2, 4, 5, and 6 In modes 1, 2, 4, 5, and 6, port D pins are automatically designated as data I/O pins. Note: Modes 2 and 6 cannot be used in the H8S/2240. Port D pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8.19. D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Figure 8.19 Port D Pin Functions (Modes 1, 2, 4, 5, and 6) Rev.3.00 Mar. 26, 2007 Page 262 of 772 REJ09B0355-0300 Section 8 I/O Ports Modes 3 and 7 In modes 3 and 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port D pin functions in modes 3 and 7 are shown in figure 8.20. PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 8.20 Port D Pin Functions (Modes 3 and 7) Rev.3.00 Mar. 26, 2007 Page 263 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.10.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 3 and 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Table 8.18 summarizes the MOS input pull-up states. Table 8.18 MOS Input Pull-Up States (Port D) Modes 1, 2, 4 to 6 3, 7 Power-On Reset OFF Hardware Standby Mode OFF Manual Reset OFF ON/OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off. Rev.3.00 Mar. 26, 2007 Page 264 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.11 8.11.1 Port E Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 8.21 shows the port E pin configuration. Port E pins PE7 / D7 PE6 / D6 PE5 / D5 Port E PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 Pin functions in modes 1, 2, 4, 5, and 6* PE7 (I/O)/ D7 (I/O) PE6 (I/O)/ D6 (I/O) PE5 (I/O)/ D5 (I/O) PE4 (I/O)/ D4 (I/O) PE3 (I/O)/ D3 (I/O) PE2 (I/O)/ D2 (I/O) PE1 (I/O)/ D1 (I/O) PE0 (I/O)/ D0 (I/O) Pin functions in modes 3 and 7* PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.21 Port E Pin Functions Rev.3.00 Mar. 26, 2007 Page 265 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.11.2 Register Configuration Table 8.19 shows the port E register configuration. Table 8.19 Port E Registers Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register Note: * Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBD H'FF6D H'FF5D H'FF74 Lower 16 bits of the address. Port E Data Direction Register (PEDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. * Modes 1, 2, 4, 5, and 6 When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller. Note: Modes 2 and 6 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 266 of 772 REJ09B0355-0300 Section 8 I/O Ports * Modes 3 and 7 Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port E Data Register (PEDR) Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port E Register (PORTE) Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 267 of 772 REJ09B0355-0300 Section 8 I/O Ports Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) when 8-bit bus mode is selected in mode 1, 2, 4, 5, or 6, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.11.3 Pin Functions Modes 1, 2, 4, 5, and 6 In modes 1, 2, 4, 5, and 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Note: Modes 2 and 6 cannot be used in the H8S/2240. Port E pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8.22. Rev.3.00 Mar. 26, 2007 Page 268 of 772 REJ09B0355-0300 Section 8 I/O Ports 8-bit bus mode PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) 16-bit bus mode D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Figure 8.22 Port E Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7 In modes 3 and 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port E pin functions in modes 3 and 7 are shown in figure 8.23. PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 8.23 Port E Pin Functions (Modes 3 and 7) Rev.3.00 Mar. 26, 2007 Page 269 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.11.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2, 4, 5, and 6 when 8-bit bus mode is selected, or in mode 3 or 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 1, 2, 4, 5, or 6 when 8-bit bus mode is selected, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Table 8.20 summarizes the MOS input pull-up states. Table 8.20 MOS Input Pull-Up States (Port E) Modes 3, 7 1, 2, 4 to 6 8-bit bus 16-bit bus OFF OFF OFF Power-On Hardware Reset Standby Mode OFF OFF Manual Reset ON/OFF Software In Other Standby Mode Operations ON/OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off. Rev.3.00 Mar. 26, 2007 Page 270 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.12 8.12.1 Port F Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK), the system clock () output pin and interrupt input pins (IRQ0 to IRQ3). The interrupt input pins (IRQ0 to IRQ3) are Schmitt-triggered inputs. Figure 8.24 shows the port F pin configuration. Port F pins PF7 / PF6 /AS PF5 /RD Port F PF4 /HWR PF3 /LWR/IRQ3 PF2 /WAIT/BREQO/IRQ2 PF1 /BACK/IRQ1 PF0 /BREQ/IRQ0 Pin functions in modes 1, 2, 4, 5, and 6* PF7 (input)/(output) AS (output) RD (output) HWR (output) LWR (output) PF2 (I/O)/WAIT (input)/BREQO (output)/IRQ2 (input) PF1 (I/O)/BACK (output)/IRQ1(input) PF0 (I/O)/BREQ (input)/IRQ0 (input) Pin functions in modes 3 and 7* PF7 (input)/ (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O)/IRQ3 (input) PF2 (I/O)/IRQ2 (input) PF1 (I/O)/IRQ1 (input) PF0 (I/O)/IRQ0 (input) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.24 Port F Pin Functions Rev.3.00 Mar. 26, 2007 Page 271 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.12.2 Register Configuration Table 8.21 shows the port F register configuration. Table 8.21 Port F Registers Name Port F data direction register Port F data register Port F register Abbreviation PFDDR PFDR PORTF R/W W R/W R Initial Value H'80/H'00* H'00 Undefined 2 Address* H'FEBE H'FF6E H'FF5E 1 Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port F Data Direction Register (PFDDR) Bit : 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4, 5, 6 Initial value : R/W : Modes 3 and 7 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2, 4, 5, and 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 2, 4, 5, and 6 Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Rev.3.00 Mar. 26, 2007 Page 272 of 772 REJ09B0355-0300 Section 8 I/O Ports The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are automatically designated as bus control outputs (AS, RD, HWR, and LWR). For pins PF2 to PF0, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 2 and 6 cannot be used in the H8S/2240. * Modes 3 and 7 Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in the case of pin PF7, the output pin. Clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port F Data Register (PFDR) Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port F Register (PORTF) Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 PF0 --* R Note: * Determined by state of pins PF7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. Rev.3.00 Mar. 26, 2007 Page 273 of 772 REJ09B0355-0300 Section 8 I/O Ports After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and in software standby mode. 8.12.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK), the system clock () output pin and interrupt input pins (IRQ0 to IRQ 3). The pin functions differ between modes 1, 2, 4, 5, and 6, and modes 3 and 7. Port F pin functions are shown in table 8.22. Table 8.22 Port F Pin Functions Pin PF7/ Selection Method and Pin Functions The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 PF7 input pin 1 output pin PF6/AS The pin function is switched as shown below according to the operating mode and bit PF6DDR. Operating Mode PF6DDR Pin function Note: * Modes 1, 2, 4, 5, 6* -- AS output pin 0 PF6 input pin Modes 3 and 7* 1 PF6 output pin Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. PF5/RD The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode PF5DDR Pin function Note: * Modes 1, 2, 4, 5, 6* -- RD output pin 0 PF5 input pin Modes 3 and 7* 1 PF5 output pin Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 274 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin PF4/HWR Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode PF4DDR Pin function Note: PF3/LWR/IRQ3 * Modes 1, 2, 4, 5, 6* -- HWR output pin 0 PF4 input pin Modes 3 and 7* 1 PF4 output pin Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. The pin function is switched as shown below according to the operating mode and bit PF3DDR. Operating Mode PF3DDR Pin function Modes 2 1, 2, 4, 5, 6* -- LWR output pin Modes 2 3 and 7* 0 1 PF3 input pin PF3 output pin 1 IRQ3 interrupt input pin* Notes: 1. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 2. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. PF2/WAIT/ BREQO/IRQ2 The pin function is switched as shown below according to the operating mode, and the BREQOE bit, WAITE bit in BCRL, and PF2DDR bit. Operating Mode BREQOE WAITE PF2DDR Pin function Modes 1, 2, 4, 5, 6* 0 2 1 Modes 3 and 7* -- 2 0 1 -- -- 0 1 -- -- 0 1 PF2 WAIT BREQO PF2 PF2 PF2 input pin output pin input pin output pin input pin output pin 1 IRQ2 interrupt input pin* Notes: 1. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 2. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 275 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin PF1/BACK/IRQ1 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, and the BRLE bit in BCRL and PF1DDR bit. Operating 2 2 Modes 3 and 7* Mode Modes 1, 2, 4, 5, 6* BRLE PF1DDR Pin function 0 0 PF1 input pin 1 PF1 output pin 1 -- BACK output pin -- 0 PF1 input pin 1 1 PF1 output pin IRQ1 interrupt input pin* Notes: 1. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 2. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. PF0/BREQ/IRQ0 The pin function is switched as shown below according to the operating mode, and the BRLE bit in BCRL and PF0DDR bit. Operating 2 2 Modes 3 and 7* Mode Modes 1, 2, 4, 5, 6* BRLE PF0DDR Pin function 0 0 PF0 input pin 1 PF0 output pin 1 -- BREQ input pin -- 0 PF0 input pin 1 1 PF0 output pin IRQ0 interrupt input pin* Notes: 1. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 2. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 276 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.13 8.13.1 Port G Overview Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3). The A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The interrupt input pins (IRQ6, IRQ7) are Schmitt-triggered inputs. Figure 8.25 shows the port G pin configuration. Port G pins Pin functions in modes 1 and 2* PG4 (input)/ CS0 (output) PG3 (I/O) PG2 (I/O) PG1 (I/O)/IRQ7 (input) PG0 (I/O)/ADTRG (input)/IRQ6 (input) PG4 /CS0 PG3 /CS1 Port G PG2 /CS2 PG1 /CS3/IRQ7 PG0 /ADTRG/IRQ6 Pin functions in modes 3 and 7* Pin functions in modes 4 to 6* PG4 (input)/ CS0 (output) PG3 (input)/ CS1 (output) PG2 (input)/ CS2 (output) PG1 (input)/ CS3 (output)/IRQ7 (input) PG0 (I/O)/ ADTRG (input)/IRQ6 (input) PG4 (I/O) PG3 (I/O) PG2 (I/O) PG1 (I/O)/IRQ7 (input) PG0 (I/O)/ ADTRG (input)/IRQ6 (input) Note: * Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Figure 8.25 Port G Pin Functions Rev.3.00 Mar. 26, 2007 Page 277 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.13.2 Register Configuration Table 8.23 shows the port G register configuration. Table 8.23 Port G Registers Name Port G data direction register Port G data register Port G register Abbreviation PGDDR PGDR PORTG R/W W R/W R Initial Value* H'00/H'10* H'00 Undefined 3 1 Address* H'FEBF H'FF6F H'FF5F 2 Notes: 1. Value of bits 4 to 0. 2. Lower 16 bits of the address. 3. Initial value depends on the mode. Port G Data Direction Register (PGDDR) Bit : 7 -- Modes 1, 4, 5 Initial value : R/W : Modes 2, 3, 6, 7 Initial value : R/W : Undefined Undefined Undefined -- -- -- 0 W 0 W 0 W 0 W 0 W Undefined Undefined Undefined -- -- -- 1 W 0 W 0 W 0 W 0 W 6 -- 5 -- 4 3 2 1 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read. PGDDR cannot be modified. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.10.4, Access Methods for Registers with Write-Only Bits. PGDDR is initialized by a power-on reset, and in hardware standby mode, to H'10 (bits 4 to 0) in modes 1, 4, and 5, and to H'00 (bits 4 to 0) in modes 2, 3, 6, and 7. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 278 of 772 REJ09B0355-0300 Section 8 I/O Ports * Modes 1, 2, 4, 5, and 6 Pins PG4 to PG1 function as bus control output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0. Pin PG0 is an output port when the corresponding PGDDR bit is set to 1, and an input port when the bit is cleared to 0. Note: Modes 2 and 6 cannot be used in the H8S/2240. * Modes 3 and 7 Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing the bit to 0 makes the pin an input port. Note: Modes 3 and 7 cannot be used in the H8S/2240. Port G Data Register (PGDR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Undefined Undefined Undefined PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 279 of 772 REJ09B0355-0300 Section 8 I/O Ports Port G Register (PORTG) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 PG4 --* R 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R 0 PG0 --* R Undefined Undefined Undefined Note: * Determined by state of pins PG4 to PG0. PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset, and in software standby mode. Rev.3.00 Mar. 26, 2007 Page 280 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.13.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3) the A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The pin functions are different in modes 1 and 2, modes 3 and 7, and modes 4 to 6. Port G pin functions are shown in table 8.24. Table 8.24 Port G Pin Functions Pin PG4/CS0 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating Mode PG4DDR Pin function Note: PG3/CS1 * Modes 1, 2, 4, 5, 6* 0 1 Modes 3 and 7* 0 1 PG4 input pin CS0 output pin PG4 input pin PG4 output pin Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. The pin function is switched as shown below according to the operating mode and bit PG3DDR. Operating Mode PG3DDR Pin function Note: * Modes 1, 2, 3, 7* 0 1 0 Modes 4 to 6* 1 PG3 input pin PG3 output pin PG3 input pin CS1 output pin Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. PG2/CS2 The pin function is switched as shown below according to the operating mode and bit PG2DDR. Operating Mode PG2DDR Pin function Note: * Modes 1, 2, 3, 7* 0 1 0 Modes 4 to 6* 1 PG2 input pin PG2 output pin PG2 input pin CS2 output pin Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. Rev.3.00 Mar. 26, 2007 Page 281 of 772 REJ09B0355-0300 Section 8 I/O Ports Pin PG1/CS3/IRQ7 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of operating mode and bit PG1DDR. Operating Mode PG1DDR Pin function Modes 1, 2, 3, 7* 0 2 Modes 4 to 6* 0 1 2 1 1 PG1 input pin PG1 output pin PG1 input pin CS3 output pin IRQ7 interrupt input pin* Notes: 1. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 2. Modes 2, 3, 6, and 7 cannot be used in the H8S/2240. PG0/ADTRG/IRQ6 The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D ADCR and bit PG0DDR. PG0DDR Pin function 0 PG0 input ADTRG input pin* 1 2 1 PG0 output IRQ6 interrupt input pin* Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1. 2. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. Rev.3.00 Mar. 26, 2007 Page 282 of 772 REJ09B0355-0300 Section 8 I/O Ports 8.14 Handling of Unused Pins Unused input pins should be fixed high or low. Generally, the input pins of CMOS products are high-impedance. Leaving unused pins open can cause the generation of intermediate levels due to peripheral noise induction. This can result in shoot-through current inside the device and cause it to malfunction. Table 8.25 lists examples of ways to handle unused pins. Table 8.25 Examples of Ways to Handle Unused Input Pins Port Name Port 1 Port 2 Port 3 Port 4 Port 5 Port A Port B Port C Port D Port E Port F Port G Connect each pin to AVcc (pull-up) or to AVss (pull-down) via a resistor. Connect each pin to Vcc (pull-up) or to Vss (pull-down) via a resistor. Pin Handling Example Connect each pin to Vcc (pull-up) or to Vss (pull-down) via a resistor. Rev.3.00 Mar. 26, 2007 Page 283 of 772 REJ09B0355-0300 Section 8 I/O Ports Rev.3.00 Mar. 26, 2007 Page 284 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Section 9 16-Bit Timer Pulse Unit (TPU) 9.1 Overview The H8S/2245 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. 9.1.1 Features * Maximum 8-pulse input/output * A total of 8 timer general registers (TGRs) are provided (four for channel 0 and two each for channels 1, and 2), each of which can be set independently as an output compare/input capture register TGRC and TGRD for channel 0 can also be used as buffer registers * Selection of 7 or 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set Maximum of 7-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channel 0 Input capture register double-buffering possible Automatic rewriting of output compare register possible * Phase counting mode settable independently for each of channels 1, and 2 Two-phase encoder pulse up/down-count possible * Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface * 13 interrupt sources For channel 0 four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1, and 2, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently Rev.3.00 Mar. 26, 2007 Page 285 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) * Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) activation * A/D converter conversion start trigger can be generated Channel 2 to 0 compare match A/input capture A signals can be used as A/D converter conversion start trigger * Module stop mode can be set As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 9.1 lists the functions of the TPU. Rev.3.00 Mar. 26, 2007 Page 286 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 Item Count clock TPU Functions (1) Channel 0 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 Channel 1 /1 /4 /16 /64 /256 TCLKA TCLKB TGR1A TGR1B -- TIOCA1 TIOCB1 Channel 2 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGR2A TGR2B -- TIOCA2 TIOCB2 General registers General registers/ buffer registers I/O pins Counter clear function Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Legend: : Possible --: Not possible TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture -- -- -- Rev.3.00 Mar. 26, 2007 Page 287 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 Item TPU Functions (2) Channel 0 Channel 1 Channel 2 DTC activation A/D converter trigger Interrupt sources TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture TGR0A compare match TGR1A compare match TGR2A compare match or input capture or input capture or input capture 5 sources * Compare match or input capture 0A * Compare match or input capture 0B * Compare match or input capture 0C * Compare match or input capture 0D * Overflow * Overflow * Underflow * Overflow * Underflow 4 sources * Compare match or input capture 1A * Compare match or input capture 1B 4 sources * Compare match or input capture 2A * Compare match or input capture 2B Rev.3.00 Mar. 26, 2007 Page 288 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the TPU. Clock input Internal clock: /1 /4 /16 /64 /256 /1024 External clock: TCLKA TCLKB TCLKC TCLKD TSTR TSYR Bus interface Control logic Common Internal data bus A/D conversion start request signal TMDR Channel 2 TSR TGRA Module data bus TIOR TIER TCR TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT Legend: TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR (H, L): TIER: TSR: TGR (A, B, C, D): TCNT: Timer I/O control registers (H, L) Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 9.1 Block Diagram of TPU TIER TCR Rev.3.00 Mar. 26, 2007 Page 289 of 772 REJ09B0355-0300 TGRA Section 9 16-Bit Timer Pulse Unit (TPU) 9.1.3 Pin Configuration Table 9.2 shows the pin configuration of the TPU. Table 9.2 Channel All TPU Pins Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin Clock input B TCLKB Input Clock input C TCLKC Input Clock input D TCLKD Input 0 Input capture/output compare match A0 Input capture/output compare match B0 Input capture/output compare match C0 Input capture/output compare match D0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 I/O I/O I/O I/O I/O I/O I/O I/O 1 Input capture/output compare match A1 Input capture/output compare match B1 2 Input capture/output compare match A2 Input capture/output compare match B2 Rev.3.00 Mar. 26, 2007 Page 290 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.1.4 Register Configuration Table 9.3 summarizes the TPU registers. Table 9.3 TPU Registers Abbreviation TCR0 TMDR0 TIOR0H TIOR0L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 2 Channel Name 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Address* H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA 1 Timer interrupt enable register 0 TIER0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 Timer interrupt enable register 1 TIER1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W 2 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Timer interrupt enable register 2 TIER2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B TSR2 TCNT2 TGR2A TGR2B R/(W) * H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF Rev.3.00 Mar. 26, 2007 Page 291 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Channel Name All Timer start register Timer synchro register Module stop control register Abbreviation TSTR TSYR MSTPCR R/W R/W R/W R/W Initial Value H'00 H'00 H'3FFF Address* H'FFC0 H'FFC1 H'FF3C 1 Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 9.2 9.2.1 Register Descriptions Timer Control Register (TCR) Channel 0: TCR0 Bit : 7 CCLR2 Initial value : R/W : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Channel 1: TCR1 Channel 2: TCR2 Bit : 7 -- Initial value : R/W : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. TCNT operation should be stopped when making TCR settings. Rev.3.00 Mar. 26, 2007 Page 292 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bits 7, 6, 5--Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Bit 7 Channel 0 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation* 1 0 0 1 1 0 1 Bit 7 Channel 1, 2 3 Bit 6 Bit 5 CCLR0 0 1 Description TCNT clearing disabled (Initial value) Reserved* CCLR1 0 0 TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1and 2. It is always read as 0 and cannot be modified. Rev.3.00 Mar. 26, 2007 Page 293 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When a both-edges count is selected, a clock divided by two from the input clock can be selected. (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, and 2, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 -- Description Count at rising edge Count at falling edge Count at both edges (Initial value) Note: Internal clock edge selection is valid when the input clock is /4 or slower. If /1 is selected as the input clock, this setting is ignored and count at falling edge of is selected. Bits 2, 1, and 0--Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 9.4 shows the clock sources that can be set for each channel. Table 9.4 TPU Clock Sources Internal Clock Channel 0 1 2 /1 /4 /16 /64 /256 /1024 External Clock TCLKA TCLKB TCLKC TCLKD Legend: : Setting Blank: No setting Rev.3.00 Mar. 26, 2007 Page 294 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 2 Channel 0 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input (Initial value) Bit 2 Channel 1 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Setting prohibited (Initial value) 1 0 1 1 0 0 1 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. Bit 2 Channel 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 (Initial value) Note: This setting is ignored when channel 2 is in phase counting mode. Rev.3.00 Mar. 26, 2007 Page 295 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Channel 1: TMDR1 Channel 2: TMDR2 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TCNT operation should be stopped when making TMDR settings. Bits 7 and 6--Reserved: Read-only bits, always read as 1. Bit 5--Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation (Initial value) Rev.3.00 Mar. 26, 2007 Page 296 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 4--Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value) Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3* 0 1 Bit 2 MD2* 0 2 Bit 1 MD1 0 Bit 0 MD0 0 1 Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- (Initial value) 1 0 1 1 0 0 1 1 0 1 1 * * * Legend: *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. Rev.3.00 Mar. 26, 2007 Page 297 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Channel 0: TIOR0L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. Rev.3.00 Mar. 26, 2007 Page 298 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bits 7 to 4-- I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. TIOR0H Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: *: Don't care * * * TGR0B is input capture register Capture input source is TIOCB0 pin Setting prohibited Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev.3.00 Mar. 26, 2007 Page 299 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TIOR0L Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D Input capture at rising edge Capture input is input source is Input capture at falling edge TIOCD0 pin capture 1 Input capture at both edges register* Setting prohibited TGR0D Output disabled is output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Legend: *: Don't care Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.3.00 Mar. 26, 2007 Page 300 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TIOR1 Bit 7 Bit 6 Bit 5 Bit 4 Channel 1 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 Legend: *: Don't care * 0 1 * * TGR1B is input capture register Capture input source is TIOCB1 pin Setting prohibited Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev.3.00 Mar. 26, 2007 Page 301 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TIOR2 Bit 7 Bit 6 Bit 5 Bit 4 Channel 2 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 Legend: *: Don't care * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev.3.00 Mar. 26, 2007 Page 302 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0-- I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. TIOR0H Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: *: Don't care * * * TGR0A is input capture register Capture input source is TIOCA0 pin Setting prohibited Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev.3.00 Mar. 26, 2007 Page 303 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TIOR0L Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * Capture input TGR0C source is is input TIOCC0 pin capture 1 register* Setting prohibited Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Output disabled TGR0C is output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Legend: *: Don't care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.3.00 Mar. 26, 2007 Page 304 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TIOR1 Bit 3 Bit 2 Bit 1 Bit 0 Channel 1 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: *: Don't care * * * TGR1A is input capture register Capture input source is TIOCA1 pin Setting prohibited Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev.3.00 Mar. 26, 2007 Page 305 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TIOR2 Bit 3 Bit 2 Bit 1 Bit 0 Channel 2 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 Legend: *: Don't care * TGR2A is input capture register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev.3.00 Mar. 26, 2007 Page 306 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Channel 1: TIER1 Channel 2: TIER2 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE 0 1 Description A/D conversion start request generation disabled A/D conversion start request generation enabled (Initial value) Bit 6--Reserved: Read-only bit, always read as 1. Rev.3.00 Mar. 26, 2007 Page 307 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 5--Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0 bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value) Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value) Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1, and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value) Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1, and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 308 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value) Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value) 9.2.5 Timer Status Register (TSR) Channel 0: TSR0 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Can only be written with 0 for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Bit : 7 TCFD Initial value : R/W : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 309 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. Bit 7--Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, and 2. In channel 0 bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value) Bit 6--Reserved: Read-only bit, always read as 1. Bit 5--Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. In channel 0 bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU 0 1 Description [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) (Initial value) Bit 4--Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 1 Description [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) (Initial value) Rev.3.00 Mar. 26, 2007 Page 310 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 3--Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1, and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 When 0 is written to TGFD after reading TGFD = 1 When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Setting conditions] Bit 2--Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1, and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 When 0 is written to TGFC after reading TGFC = 1 When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Setting conditions] Rev.3.00 Mar. 26, 2007 Page 311 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Bit 1--Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 When 0 is written to TGFB after reading TGFB = 1 When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Setting conditions] Bit 0--Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 When 0 is written to TGFA after reading TGFA = 1 When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Setting conditions] Rev.3.00 Mar. 26, 2007 Page 312 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode. In other cases they function as up-counters. The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 9.2.7 Bit Timer General Register (TGR) : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 8 TGR registers, four for channel 0 and two each for channels 1, and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD. Rev.3.00 Mar. 26, 2007 Page 313 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.8 Bit Timer Start Register (TSTR) : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Initial value : R/W : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TSTR is initialized to H'00 by a reset, and in hardware standby mode. TCNT counter operation should be stopped when setting the operating mode in TMDR or the TCNT count clock in TCR. Bits 7 and 3--Reserved: Should always be written with 0. Bits 2 to 0--Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value) n = 2 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. Rev.3.00 Mar. 26, 2007 Page 314 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.9 Bit Timer Synchro Register (TSYR) : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Initial value : R/W : TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 3--Reserved: Should always be written with 0. Bits 2 to 0--Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels* , and 2 synchronous clearing through counter clearing on another channel* are possible. Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Bit n SYNCn 0 1 Description TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Note: n = 2 to 0 1 Rev.3.00 Mar. 26, 2007 Page 315 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 18.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 13--Module Stop (MSTP13): Specifies the TPU module stop mode. Bit 13 MSTP13 0 1 Description TPU module stop mode cleared TPU module stop mode set (Initial value) Rev.3.00 Mar. 26, 2007 Page 316 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.3 9.3.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 9.2. Internal data bus H Bus master Module data bus L Bus interface TCNTH TCNTL Figure 9.2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 9.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 9.3 to 9.5. Rev.3.00 Mar. 26, 2007 Page 317 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Internal data bus H Bus master Module data bus L Bus interface TCR Figure 9.3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TMDR Figure 9.4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TCR TMDR Figure 9.5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] Rev.3.00 Mar. 26, 2007 Page 318 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4 9.4.1 Operation Overview Operation in each mode is outlined below. Normal Operation Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. * When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. PWM Mode In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Rev.3.00 Mar. 26, 2007 Page 319 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, and 2. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input. 9.4.2 Basic Functions Counter Operation When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. Example of count operation setting procedure: Figure 9.6 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the count operation. Operation selection Select counter clock [1] Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] Start count operation [5] Figure 9.6 Example of Counter Operation Setting Procedure Rev.3.00 Mar. 26, 2007 Page 320 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Free-running count operation and periodic count operation: Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 9.7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 9.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 9.8 illustrates periodic counter operation. Rev.3.00 Mar. 26, 2007 Page 321 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 9.8 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. Example of setting procedure for waveform output by compare match: Figure 9.9 shows an example of the setting procedure for waveform output by compare match [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [1] Output selection Select waveform output mode [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set output timing [2] Start count operation [3] Figure 9.9 Example Of Setting Procedure For Waveform Output By Compare Match Rev.3.00 Mar. 26, 2007 Page 322 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Examples of waveform output operation: Figure 9.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 9.10 Example of 0 Output/1 Output Operation Figure 9.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 9.11 Example of Toggle Output Operation Rev.3.00 Mar. 26, 2007 Page 323 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. Example of input capture operation setting procedure: Figure 9.12 shows an example of the input capture operation setting procedure. [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [1] Input selection Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 9.12 Example of Input Capture Operation Setting Procedure Rev.3.00 Mar. 26, 2007 Page 324 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Example of input capture operation: Figure 9.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 9.13 Example of Input Capture Operation 9.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. Rev.3.00 Mar. 26, 2007 Page 325 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure Figure 9.14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing sourcegeneration channel? Yes Select counter clearing source Start count No [3] [5] Set synchronous counter clearing Start count [4] [5] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 9.14 Example of Synchronous Operation Setting Procedure Rev.3.00 Mar. 26, 2007 Page 326 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 9.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 9.4.5, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time TIOC0A TIOC1A TIOC2A Figure 9.15 Example of Synchronous Operation Rev.3.00 Mar. 26, 2007 Page 327 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.4 Buffer Operation Buffer operation, provided for channel 0 enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 9.5 shows the register combinations used in buffer operation. Table 9.5 Channel 0 Register Combinations in Buffer Operation Timer General Register TGR0A TGR0B Buffer Register TGR0C TGR0D When TGR is an output compare register: When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.16. Compare match signal Buffer register Timer general register Comparator TCNT Figure 9.16 Compare Match Buffer Operation When TGR is an input capture register: When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9.17. Rev.3.00 Mar. 26, 2007 Page 328 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Input capture signal Timer general register Buffer register TCNT Figure 9.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 9.18 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 9.18 Example of Buffer Operation Setting Procedure Rev.3.00 Mar. 26, 2007 Page 329 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation When TGR is an output compare register: Figure 9.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 9.4.5, PWM Modes. TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 9.19 Example of Buffer Operation (1) Rev.3.00 Mar. 26, 2007 Page 330 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) When TGR is an input capture register: Figure 9.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 9.20 Example of Buffer Operation (2) 9.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. Rev.3.00 Mar. 26, 2007 Page 331 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 9.6. Table 9.6 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGR0A TGR0B TGR0C TGR0D 1 TGR1A TGR1B 2 TGR2A TGR2B TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev.3.00 Mar. 26, 2007 Page 332 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure Figure 9.21 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [1] PWM mode Select counter clock Select counter clearing source [2] [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Select waveform output level [3] Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 9.21 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation Figure 9.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 output is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. Rev.3.00 Mar. 26, 2007 Page 333 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 9.22 Example of PWM Mode Operation (1) Figure 9.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers, to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty. Counter cleared by TGR1B compare match TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 9.23 Example of PWM Mode Operation (2) Rev.3.00 Mar. 26, 2007 Page 334 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRA TGRB rewritten TGRB H'0000 0% duty TGRB rewritten TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 9.24 Example of PWM Mode Operation (3) Rev.3.00 Mar. 26, 2007 Page 335 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 9.7 shows the correspondence between external clock pins and channels. Table 9.7 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure Figure 9.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 9.25 Example of Phase Counting Mode Setting Procedure Rev.3.00 Mar. 26, 2007 Page 336 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1: Figure 9.26 shows an example of phase counting mode 1 operation, and table 9.8 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 9.26 Example of Phase Counting Mode 1 Operation Table 9.8 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count Rev.3.00 Mar. 26, 2007 Page 337 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Phase counting mode 2: Figure 9.27 shows an example of phase counting mode 2 operation, and table 9.9 summarizes the TCNT up/down-count conditions. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Up-count Down-count Time Figure 9.27 Example of Phase Counting Mode 2 Operation Table 9.9 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count Up-count Don't care Rev.3.00 Mar. 26, 2007 Page 338 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3: Figure 9.28 shows an example of phase counting mode 3 operation, and table 9.10 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 9.28 Example of Phase Counting Mode 3 Operation Table 9.10 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Up-count Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Rev.3.00 Mar. 26, 2007 Page 339 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Phase counting mode 4: Figure 9.29 shows an example of phase counting mode 4 operation, and table 9.11 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 9.29 Example of Phase Counting Mode 4 Operation Table 9.11 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev.3.00 Mar. 26, 2007 Page 340 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.5 9.5.1 Interrupts Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 9.12 lists the TPU interrupt sources. Table 9.12 TPU Interrupts Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Description TGR0A input capture/compare match TGR0B input capture/compare match TGR0C input capture/compare match TGR0D input capture/compare match TCNT0 overflow TGR1A input capture/compare match TGR1B input capture/compare match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare match TGR2B input capture/compare match TCNT2 overflow TCNT2 underflow DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev.3.00 Mar. 26, 2007 Page 341 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 8 input capture/compare match interrupts, four for channel 0, and two each for channels 1, and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a particular channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1, and 2. 9.5.2 DTC Activation DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, Data Transfer Controller. A total of 8 TPU input capture/compare match interrupts can be used as DTC activation sources, four for channels 0, and two each for channels 1, and 2. 9.5.3 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TFGA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev.3.00 Mar. 26, 2007 Page 342 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.6 9.6.1 Operation Timing Input/Output Timing TCNT Count Timing Figure 9.30 shows TCNT count timing in internal clock operation, and figure 9.31 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 9.30 Count Timing in Internal Clock Operation External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 9.31 Count Timing in External Clock Operation Rev.3.00 Mar. 26, 2007 Page 343 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.32 shows output compare output timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 9.32 Output Compare Output Timing Rev.3.00 Mar. 26, 2007 Page 344 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture Signal Timing Figure 9.33 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 9.33 Input Capture Input Signal Timing Rev.3.00 Mar. 26, 2007 Page 345 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 9.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.35 shows the timing when counter clearing by input capture occurrence is specified. Compare match signal Counter clear signal N H'0000 TCNT TGR N Figure 9.34 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal N H'0000 TCNT TGR N Figure 9.35 Counter Clear Timing (Input Capture) Rev.3.00 Mar. 26, 2007 Page 346 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 9.36 and 9.37 show the timing in buffer operation. TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 9.36 Buffer Operation Timing (Compare Match) Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 9.37 Buffer Operation Timing (Input Capture) Rev.3.00 Mar. 26, 2007 Page 347 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 9.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 9.38 TGI Interrupt Timing (Compare Match) Rev.3.00 Mar. 26, 2007 Page 348 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture Figure 9.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 9.39 TGI Interrupt Timing (Input Capture) Rev.3.00 Mar. 26, 2007 Page 349 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 9.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 9.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 9.40 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 9.41 TCIU Interrupt Setting Timing Rev.3.00 Mar. 26, 2007 Page 350 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by the CPU, and figure 9.43 shows the timing for status flag clearing by the DTC. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 9.42 Timing for Status Flag Clearing by CPU DTC read cycle T1 T2 DTC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 9.43 Timing for Status Flag Clearing by DTC Activation Rev.3.00 Mar. 26, 2007 Page 351 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) 9.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 18, Power-Down Modes. Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.44 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 9.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev.3.00 Mar. 26, 2007 Page 352 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Caution on Period Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= (N + 1) Where f: Counter frequency : Operating frequency N: TGR set value Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.45 shows the timing in this case. TCNT write cycle T1 T2 Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 9.45 Contention between TCNT Write and Clear Operations Rev.3.00 Mar. 26, 2007 Page 353 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.46 shows the timing in this case. TCNT write cycle T1 T2 Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 9.46 Contention between TCNT Write and Increment Operations Rev.3.00 Mar. 26, 2007 Page 354 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is prohibited. A compare match does not occur even if the same value as before is written. Figure 9.47 shows the timing in this case. TGR write cycle T1 T2 Address TGR address Write signal Compare match signal TCNT N N+1 Prohibited TGR N TGR write data M Figure 9.47 Contention between TGR Write and Compare Match Rev.3.00 Mar. 26, 2007 Page 355 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 9.48 shows the timing in this case. TGR write cycle T1 T2 Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 9.48 Contention between Buffer Register Write and Compare Match Rev.3.00 Mar. 26, 2007 Page 356 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9.49 shows the timing in this case. TGR read cycle T1 T2 Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 9.49 Contention between TGR Read and Input Capture Rev.3.00 Mar. 26, 2007 Page 357 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.50 shows the timing in this case. TGR write cycle T1 T2 Address TGR address Write signal Input capture signal TCNT M TGR M Figure 9.50 Contention between TGR Write and Input Capture Rev.3.00 Mar. 26, 2007 Page 358 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.51 shows the timing in this case. Buffer register write cycle T1 T2 Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 9.51 Contention between Buffer Register Write and Input Capture Rev.3.00 Mar. 26, 2007 Page 359 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. TCNT input clock TCNT Counter clear signal TGF flag Prohibited TCFV flag H'FFFF H'0000 Figure 9.52 Contention between Overflow and Counter Clearing Rev.3.00 Mar. 26, 2007 Page 360 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.53 shows the operation timing in the case of contention between a TCNT write and overflow. TCNT write cycle T1 T2 Address TCNT address Write signal TCNT write data H'FFFF M TCNT TCFV flag Prohibited Figure 9.53 Contention between TCNT Write and Overflow Multiplexing of I/O Pins In the H8S/2245 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev.3.00 Mar. 26, 2007 Page 361 of 772 REJ09B0355-0300 Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 362 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Section 10 8-Bit Timers 10.1 Overview The H8S/2245 Group includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 10.1.1 Features * Selection of four clock sources The counters can be driven by one of three internal clock signals (/8, /64, or /8192) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal. * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output. * Provision for cascading of two channels Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode). Channel 1 can be used to count channel 0 compare matches (compare match count mode). * Three independent interrupts Compare match A and B and overflow interrupts can be requested independently. * Module stop mode can be set As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting module stop mode. Rev.3.00 Mar. 26, 2007 Page 363 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the 8-bit timer module. External clock source TMCI0 TMCI1 Internal clock sources /8 /64 /8192 Clock select Clock 1 Clock 0 TCORA0 Compare match A1 Compare match A0 Comparator A0 Overflow 1 Overflow 0 Clear 0 Compare match B1 Compare match B0 Comparator B0 TCORA1 Comparator A1 TMO0 TMRI0 TCNT0 Clear 1 TCNT1 Comparator B1 TMO1 TMRI1 Control logic TCORB0 TCORB1 TCSR0 TCSR1 TCR0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals Legend: TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0: Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0 TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1: TCR1 Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1 Figure 10.1 Block Diagram of 8-Bit Timer Rev.3.00 Mar. 26, 2007 Page 364 of 772 REJ09B0355-0300 Internal bus Section 10 8-Bit Timers 10.1.3 Pin Configuration Table 10.1 summarizes the input and output pins of the 8-bit timer. Table 10.1 Input and Output Pins of 8-Bit Timer Channel 0 Name Timer output pin 0 Timer clock input pin 0 Timer reset input pin 0 1 Timer output pin 1 Timer clock input pin 1 Timer reset input pin 1 Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Outputs at compare match Inputs external clock for counter Inputs external reset to counter Outputs at compare match Inputs external clock for counter Inputs external reset to counter 10.1.4 Register Configuration Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers Channel 0 Name Timer control register 0 Abbreviation TCR0 R/W R/W R/(W)* R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W 2 2 Initial Value H'00 H'00 H'FF H'FF H'00 H'00 H'10 H'FF H'FF H'00 H'3FFF Address* H'FFB0 H'FFB2 H'FFB4 H'FFB6 H'FFB8 H'FFB1 H'FFB3 H'FFB5 H'FFB7 H'FFB9 H'FF3C 1 Timer control/status register 0 TCSR0 Time constant register A0 Time constant register B0 Timer counter 0 1 Timer control register 1 TCORA0 TCORB0 TCNT0 TCR1 Timer control/status register 1 TCSR1 Time constant register A1 Time constant register B1 Timer counter 1 All Module stop control register TCORA1 TCORB1 TCNT1 MSTPCR Notes: 1. Lower 16 bits of the address 2. Only 0 can be written to bits 7 to 5, to clear these flags. Rev.3.00 Mar. 26, 2007 Page 365 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Each pair of registers for channel 0 and channel 1 is a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word transfer instruction. 10.2 10.2.1 Register Descriptions Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 TCNT1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Bit : 15 0 14 0 13 0 12 0 11 0 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 of TCR. The CPU can read or write to TCNT0 and TCNT1 at all times. TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word transfer instruction. TCNT0 and TCNT1 can be cleared by an external reset input or by a compare match signal. Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 of TCR. When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 366 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) TCORA0 TCORA1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 1 14 1 13 1 12 1 11 1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag of TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output can be freely controlled by these compare match signals and the settings of output select bits OS1 and OS0 of TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORB1 4 1 3 1 2 1 1 1 0 1 Initial value: R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag of TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORB write cycle. The timer output can be freely controlled by these compare match signals and the settings of output select bits OS3 and OS2 of TCSR. TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 367 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.2.4 Bit Time Control Registers 0 and 1 (TCR0, TCR1) : 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value: R/W : TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at which TCNT is cleared, and enable interrupts. TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode. For details of this timing, see section 10.3, Operation. Bit 7--Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1. Bit 7 CMIEB 0 1 Description CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled (Initial value) Bit 6--Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1. Bit 6 CMIEA 0 1 Description CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled (Initial value) Bit 5--Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag of TCSR is set to 1. Bit 5 OVIE 0 1 Description OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 368 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared: by compare match A or B, or by an external reset input. Bit 4 CCLR1 0 Bit 3 CCLR0 0 1 1 0 1 Description Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (): /8, /64, and /8192. The falling edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1. Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Clock input disabled Internal clock, counted at falling edge of /8 Internal clock, counted at falling edge of /64 Internal clock, counted at falling edge of /8192 For channel 0: count at TCNT1 overflow signal* For channel 1: count at TCNT0 compare match A* External clock, counted at rising edge External clock, counted at falling edge External clock, counted at both rising and falling edges (Initial value) If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Rev.3.00 Mar. 26, 2007 Page 369 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.2.5 TCSR0 Bit Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1) : 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Initial value : R/W : TCSR1 Bit : 7 CMFB Initial value : R/W : 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Note: * Only 0 can be written to bits 7 to 5, to clear these flags. TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode. Bit 7--Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB 0 Description [Clearing conditions] * * 1 Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 (Initial value) [Setting condition] Set when TCNT matches TCORB Rev.3.00 Mar. 26, 2007 Page 370 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Bit 6--Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match. Bit 6 CMFA 0 Description [Clearing conditions] * * 1 Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 (Initial value) [Setting condition] Set when TCNT matches TCORA Bit 5--Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 OVF 0 1 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 (Initial value) Bit 4--A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare-match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified. Bit 4 ADTE 0 1 Description A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 371 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare match of TCOR and TCNT. Bits OS3 and OS2 select the effect of compare match B on the output level, bits OS1 and OS0 select the effect of compare match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: toggle output > 1 output > 0 output. If compare matches occur simultaneously, the output changes according to the compare match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare match event occurs. Bit 3 OS3 0 Bit 2 OS2 0 1 1 0 1 Description No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) (Initial value) Bit 1 OS1 0 Bit 0 OS0 0 1 Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value) 1 0 1 Rev.3.00 Mar. 26, 2007 Page 372 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 18.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 12--Module Stop (MSTP12): Specifies the 8-bit timer stop mode. Bit 12 MSTP12 0 1 Description 8-bit timer module stop mode cleared 8-bit timer module stop mode set (Initial value) Rev.3.00 Mar. 26, 2007 Page 373 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.3 10.3.1 Operation TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock Three different internal clock signals (/8, /64, or /8192) divided from the system clock () can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10.2 shows the count timing. Internal clock Clock input to TCNT TCNT N-1 N N+1 Figure 10.2 Count Timing for Internal Clock Input External Clock Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 10.3 shows the timing of incrementation at both edges of an external clock signal. Rev.3.00 Mar. 26, 2007 Page 374 of 772 REJ09B0355-0300 Section 10 8-Bit Timers External clock input Clock input to TCNT TCNT N-1 N N+1 Figure 10.3 Count Timing for External Clock Input 10.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB) The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 10.4 shows this timing. TCNT N N+1 TCOR Compare match signal N CMF Figure 10.4 Timing of CMF Setting Rev.3.00 Mar. 26, 2007 Page 375 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Timer output timing When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 10.5 shows the timing when the output is set to toggle at compare match A. Compare match A signal Timer output pin Figure 10.5 Timing of Timer Output Timing of Compare Match Clear The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.6 shows the timing of this operation. Compare match signal TCNT N H'00 Figure 10.6 Timing of Compare Match Clear Rev.3.00 Mar. 26, 2007 Page 376 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7 shows the timing of this operation. External reset input pin Clear signal TCNT N-1 N H'00 Figure 10.7 Timing of External Reset 10.3.4 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 10.8 shows the timing of this operation. TCNT H'FF H'00 Overflow signal OVF Figure 10.8 Timing of OVF Setting Rev.3.00 Mar. 26, 2007 Page 377 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare match flags The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs. The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set. The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare match conditions. Compare Match Counter Mode When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A's for channel 0. Channels 1 and 0 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Rev.3.00 Mar. 26, 2007 Page 378 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Note on Usage If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes. 10.4 10.4.1 Interrupt Sources Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 10.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 10.3 8-Bit Timer Interrupt Sources Channel Interrupt Source CMIA0 CMIB0 OVI0 1 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Priority High 0 Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 10.4.2 A/D Converter Activation The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev.3.00 Mar. 26, 2007 Page 379 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 10.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 10.9 Example of Pulse Output Rev.3.00 Mar. 26, 2007 Page 380 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 10.6.1 Setting Module Stop Mode The TMR is enabled or disabled by setting the module stop control register. In the initial state, the TMR is disabled. After the module stop mode is canceled, registers can be accessed. For details, see section 18, Power-Down Modes. 10.6.2 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 10.10 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 10.10 Contention between TCNT Write and Clear Rev.3.00 Mar. 26, 2007 Page 381 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.6.3 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 10.11 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 10.11 Contention between TCNT Write and Increment Rev.3.00 Mar. 26, 2007 Page 382 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.6.4 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare match event occurs. Figure 10.12 shows this operation. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 10.12 Contention between TCOR Write and Compare Match Rev.3.00 Mar. 26, 2007 Page 383 of 772 REJ09B0355-0300 Section 10 8-Bit Timers 10.6.5 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 10.4. Table 10.4 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 10.6.6 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 10.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 10.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks. Rev.3.00 Mar. 26, 2007 Page 384 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Table 10.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from 1 low to low* Clock before switchover Clock after switchover TCNT clock No. 1 TCNT N CKS bit write N+1 2 Switching from 2 low to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from 3 high to low* Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 CKS bit write N+2 Rev.3.00 Mar. 26, 2007 Page 385 of 772 REJ09B0355-0300 Section 10 8-Bit Timers Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock No. 4 TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 10.6.7 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev.3.00 Mar. 26, 2007 Page 386 of 772 REJ09B0355-0300 Section 11 Watchdog Timer Section 11 Watchdog Timer 11.1 Overview The H8S/2245 Group has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2245 Group. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 11.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode * WDTOVF output when in watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire H8S/2245 Group is reset at the same time. This internal reset can be a power-on reset or a manual reset. * Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt. * Choice of eight counter clock sources. Rev.3.00 Mar. 26, 2007 Page 387 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select WDTOVF Internal reset signal* Reset control /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources RSTCSR TCNT TSCR Module bus Bus interface WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected. Figure 11.1 Block Diagram of WDT Rev.3.00 Mar. 26, 2007 Page 388 of 772 REJ09B0355-0300 Internal bus Section 11 Watchdog Timer 11.1.3 Pin Configuration Table 11.1 describes the WDT output pin. Table 11.1 WDT Pin Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs counter overflow signal in watchdog timer mode 11.1.4 Register Configuration The WDT has three registers, as summarized in table 11.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 11.2 WDT Registers Address* Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W R/(W)* R/W R/(W)* 3 3 1 Initial Value H'18 H'00 H'1F Write* 2 Read H'FFBC H'FFBD H'FFBF H'FFBC H'FFBC H'FFBE Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 11.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. Rev.3.00 Mar. 26, 2007 Page 389 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.2 11.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. 11.2.2 Bit Timer Control/Status Register (TCSR) : 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: * Can only be written with 0 for flag clearing. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. Rev.3.00 Mar. 26, 2007 Page 390 of 772 REJ09B0355-0300 Section 11 Watchdog Timer Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF 0 1 Note: * Description [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF* [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read at least twice. (Initial value) Bit 6--Timer Mode Select (WT/IT Selects whether the WDT is used as a watchdog timer or IT): IT interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal when TCNT overflows. Bit 6 WT/IT IT 0 1 Note: * Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) Watchdog timer: Generates the WDTOVF signal when TCNT overflows* For details of the case where TCNT overflows in watchdog timer mode, see section 11.2.3, Reset Control/Status Register (RSTCSR). Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) Bits 4 and 3--Reserved: Read-only bits, always read as 1. Rev.3.00 Mar. 26, 2007 Page 391 of 772 REJ09B0355-0300 Section 11 Watchdog Timer Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (), for input to TCNT. Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Clock /2 (initial value) /64 /128 /512 /2048 /8192 /32768 /131072 Overflow period (when = 20 MHz)* 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 11.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : R/W : Note: * Can only be written with 0 for flag clearing. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. Rev.3.00 Mar. 26, 2007 Page 392 of 772 REJ09B0355-0300 Section 11 Watchdog Timer Bit 7--Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 1 Description [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer operation (Initial value) Bit 6--Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2245 Group if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Note: * Description Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows The modules within the H8S/2245 Group are not reset, but TCNT and TCSR within the WDT are reset. (Initial value) Bit 5--Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of resets, see section 4, Exception Handling. Bit 5 RSTS 0 1 Description Power-on reset Manual reset (Initial value) Bits 4 to 0--Reserved: Read-only bits, always read as 1. Rev.3.00 Mar. 26, 2007 Page 393 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 11.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR (see figure 11.2). TCNT write 15 Address: H'FFBC H'5A 87 Write data 0 TCSR write 15 Address: H'FFBC H'A5 87 Write data 0 Figure 11.2 Format of Data Written to TCNT and TCSR Rev.3.00 Mar. 26, 2007 Page 394 of 772 REJ09B0355-0300 Section 11 Watchdog Timer Writing to RSTCSR RSTCSR must be written to by word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 11.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF flag, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF flag. Writing 0 to WOVF bit 15 Address: H'FFBE H'A5 87 H'00 0 Writing to RSTE and RSTS bits 15 Address: H'FFBE H'5A 87 Write data 0 Figure 11.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. Rev.3.00 Mar. 26, 2007 Page 395 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.3 11.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This is shown in figure 11.4. This WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2245 Group internally is generated at the same time as the WDTOVF signal. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF flag in RSTCSR is cleared to 0. Rev.3.00 Mar. 26, 2007 Page 396 of 772 REJ09B0355-0300 Section 11 Watchdog Timer TCNT count WDT overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written to TCNT WOVF = 1 WDTOVF and internal reset are generated WT/IT = 1 H'00 written TME = 1 to TCNT Time WDTOVF signal 132 states*2 Internal reset signal*1 Legend: WT/IT : Timer mode select bit TME : Timer enable bit WOVF : Watchdog timer overflow 518 states Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0 Figure 11.4 Watchdog Timer Operation Rev.3.00 Mar. 26, 2007 Page 397 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 11.5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 11.5 Interval Timer Operation Rev.3.00 Mar. 26, 2007 Page 398 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 11.6. TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 11.6 Timing of Setting of OVF Rev.3.00 Mar. 26, 2007 Page 399 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2245 Group chip. Figure 11.7 shows the timing in this case. TCNT H'FF H'00 Overflow signal (internal signal) WOVF WDTOVF signal Internal reset signal 132 states 518 states Figure 11.7 Timing of Setting of WOVF 11.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Rev.3.00 Mar. 26, 2007 Page 400 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.5 11.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock pulse TCNT N M Counter write data Figure 11.8 Contention between TCNT Write and Increment 11.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. Rev.3.00 Mar. 26, 2007 Page 401 of 772 REJ09B0355-0300 Section 11 Watchdog Timer 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 11.5.4 System Reset by WDTOVF Signal If the WDTOVF output signal is input to the RES pin of the H8S/2245 Group, the H8S/2245 Group will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 11.9. H8S/2245 RES Reset input Reset signal to entire system WDTOVF Figure 11.9 Circuit for System Reset by WDTOVF Signal (Example) 11.5.5 Internal Reset in Watchdog Timer Mode The H8S/2245 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 11.5.6 OVF Flag Clearing in Interval Timer Mode When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag. Rev.3.00 Mar. 26, 2007 Page 402 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) 12.1 Overview The H8S/2245 Group is equipped with a 3-channel serial communication interface (SCI). All three channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 12.1.1 Features SCI features are listed below. * Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode Serial data communication executed using asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length: Stop bit length: Parity: Multiprocessor bit: Break detection: Clocked Synchronous mode Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length: 8 bits Receive error detection: Overrun errors detected Rev.3.00 Mar. 26, 2007 Page 403 of 772 REJ09B0355-0300 7 or 8 bits 1 or 2 bits Even, odd, or none 1 or 0 Break can be detected by reading the RxD pin level directly in case of a framing error Receive error detection: Parity, overrun, and framing errors Section 12 Serial Communication Interface (SCI) * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * On-chip baud rate generator allows any bit rate to be selected * Choice of LSB-first or MSB-first transfer (8 bits length) Can be selected regardless of the communication mode* Note: * Descriptions in this section refer to LSB-first transfer. * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources Four interrupt sources -- transmit-data-empty, transmit-end, receive-data-full, and receive error -- that can issue requests independently The transmit-data-empty interrupt and receive data full interrupts can activate data transfer controller (DTC) to execute data transfer * Module stop mode can be set As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. Rev.3.00 Mar. 26, 2007 Page 404 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SCMR SSR SCR SMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock RxD RSR TSR TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend: SCMR : Smart Card mode register RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register Figure 12.1 Block Diagram of SCI Rev.3.00 Mar. 26, 2007 Page 405 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.1.3 Pin Configuration Table 12.1 shows the serial pins for each SCI channel. Table 12.1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev.3.00 Mar. 26, 2007 Page 406 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.1.4 Register Configuration The SCI has the internal registers shown in table 12.2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/receiver. Table 12.2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Abbreviation SMR 0 BRR 0 SCR 0 TDR 0 SSR 0 RDR 0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C 1 Module stop control register MSTPCR Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 407 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.2 12.2.1 Bit R/W Register Descriptions Receive Shift Register (RSR) : : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 12.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode. Rev.3.00 Mar. 26, 2007 Page 408 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.2.3 Bit R/W Transmit Shift Register (TSR) : : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 12.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode. Rev.3.00 Mar. 26, 2007 Page 409 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.2.5 Bit Serial Mode Register (SMR) : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7--Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode A as the SCI operating mode. Bit 7 C/A A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. (Initial value) Rev.3.00 Mar. 26, 2007 Page 410 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. (Initial value) Bit 4--Parity Mode (O/E): Selects either even or odd parity for use in parity addition and E checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E E 0 1 Description Even parity* Odd parity* 2 1 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev.3.00 Mar. 26, 2007 Page 411 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Rev.3.00 Mar. 26, 2007 Page 412 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from , /4, /16, and /64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 12.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description clock /4 clock /16 clock /64 clock (Initial value) 12.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Note: * Description Transmit data empty interrupt (TXI) requests disabled* Transmit data empty interrupt (TXI) requests enabled TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. (Initial value) Rev.3.00 Mar. 26, 2007 Page 413 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Note: * Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* Transmission enabled* 1 (Initial value) 2 Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled* Reception enabled* 1 (Initial value) 2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Rev.3.00 Mar. 26, 2007 Page 414 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When MPB = 1 data is received (Initial value) Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Note: * Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. (Initial value) Rev.3.00 Mar. 26, 2007 Page 415 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 12.9. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output* Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input 3 3 2 Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Rev.3.00 Mar. 26, 2007 Page 416 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] * * 1 * * Note: * When 0 is written to TDRE after reading TDRE = 1 When the DTC* is activated by a TXI interrupt and write data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Setting conditions] DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 417 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] * * 1 When 0 is written to RDRF after reading RDRF = 1 When the DTC* is activated by an RXI interrupt and read data from RDR (Initial value) [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Notes: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 1 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1* 2 1 (Initial value)* Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Rev.3.00 Mar. 26, 2007 Page 418 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 1 Description [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, 2 and the stop bit is 0* Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not 2 match the parity setting (even or odd) specified by the O/E bit in SMR* Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Rev.3.00 Mar. 26, 2007 Page 419 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * 1 When the DTC* is activated by a TXI interrupt and write data to TDR (Initial value) [Setting conditions] * When the TE bit in SCR is 0 * Note: * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Bit 1--Multiprocessor bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Note: * Description [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. (Initial value)* Rev.3.00 Mar. 26, 2007 Page 420 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in clocked synchronous mode, when multiprocessor format is not used, and when the operation is not transmission. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 12.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR settings in clocked synchronous mode. Rev.3.00 Mar. 26, 2007 Page 421 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 1 1 0 0 0 0 0 0 -- -- -- 2.097152 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) n 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) n N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- -0.04 1 0.21 0.21 0.21 1 0 0 -0.26 1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 1 1 0 0 0 0 0 0 0 -- -0.70 0 1.14 0 -2.48 0 -2.48 0 -- -- -- 0 -- 0 (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 -1.70 0 0.00 0 Rev.3.00 Mar. 26, 2007 Page 422 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) n 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) n N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- -0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 -0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 2 1 1 0 0 0 0 0 0 -- -2.34 0 -2.34 0 0.00 0 -2.34 0 (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) n N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) n N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 n 2 2 2 1 1 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 -0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 -0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -1.36 0 1.73 0.00 1.73 0 0 0 -2.34 0 0.00 0 -1.70 0 0.00 0 -2.34 0 Rev.3.00 Mar. 26, 2007 Page 423 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) n 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 2 2 1 1 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 -0.17 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -0.93 0 -0.93 0 0.00 -- 0 0 -1.70 0 0.00 0 (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) n 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 2 2 1 1 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 -0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -0.69 0 1.02 0.00 0 0 -1.70 0 0.00 0 -2.34 0 Legend: --: Can be set, but there will be a degree of error. Note: As far as possible, the setting should be made so that the error is no more than 1%. Rev.3.00 Mar. 26, 2007 Page 424 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 -- 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 -- n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 -- -- 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 -- -- n -- -- -- -- 2 1 1 0 0 0 0 0 0 0 0 20 N -- -- -- -- 124 249 124 199 99 49 19 9 4 1 0* Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transmission/reception is not possible. Note: As far as possible, the setting should be made so that the error is no more than 1%. Rev.3.00 Mar. 26, 2007 Page 425 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) The BRR setting is found from the following formulas. Asynchronous mode: N= 64 x 2 2n-1 xB x 10 - 1 6 Clocked synchronous mode: N= Where B: N: : n: 8x2 2n-1 xB x 10 - 1 6 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { x 10 6 2n-1 (N + 1) x B x 64 x 2 - 1} x 100 Rev.3.00 Mar. 26, 2007 Page 426 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.3.00 Mar. 26, 2007 Page 427 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Rev.3.00 Mar. 26, 2007 Page 428 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 Rev.3.00 Mar. 26, 2007 Page 429 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.2.9 Bit Smart Card Mode Register (SCMR) : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. With an 8-bit length, LSB-first or MSB-first transfer can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see 13.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. The transfer format is valid for 8-bit data. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2--Smart Card Data Invert (SINV): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Rev.3.00 Mar. 26, 2007 Page 430 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 18.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Module Stop (MSTP7): Specifies the SCI channel 2 module stop mode. Bit 7 MSTP7 0 1 Description SCI channel 2 module stop mode cleared SCI channel 2 module stop mode set (Initial value) Bit 6--Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6 0 1 Description SCI channel 1 module stop mode cleared SCI channel 1 module stop mode set (Initial value) Bit 5--Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5 0 1 Description SCI channel 0 module stop mode cleared SCI channel 0 module stop mode set (Initial value) Rev.3.00 Mar. 26, 2007 Page 431 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.3 12.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 12.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 12.9. Asynchronous mode: * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked synchronous mode: * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock Rev.3.00 Mar. 26, 2007 Page 432 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 1 1 0 1 0 1 1 -- -- 1 -- -- -- -- -- Bit 3 STOP 0 1 0 1 0 1 0 1 0 1 0 1 -- 8-bit data Clocked synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data 7-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Data Length 8-bit data SCI Transfer Format Multiprocessor Bit No Parity Bit No Yes Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Table 12.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synchronous mode Internal Mode Asynchronous mode SCI Transmit/Receive clock Clock Source Internal SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs the serial clock External Inputs the serial clock Rev.3.00 Mar. 26, 2007 Page 433 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 D7 MSB 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev.3.00 Mar. 26, 2007 Page 434 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 12.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S: STOP: P: MPB: Start bit Stop bit Parity bit Multiprocessor bit Rev.3.00 Mar. 26, 2007 Page 435 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI initialization (asynchronous mode): Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. Figure 12.4 shows a sample SCI initialization flowchart. Rev.3.00 Mar. 26, 2007 Page 436 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Note: * Perform this set operation with the RxD pin in the 1 state. If the RE bit is set to 1 with the RxD pin in the 0 state, it may be misinterpreted as a start bit. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE* bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Figure 12.4 Sample SCI Initialization Flowchart Rev.3.00 Mar. 26, 2007 Page 437 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Serial data transmission (asynchronous mode): Figure 12.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC* is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Note: * The case, in which the DTC automatically checks and clears the TDRE flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the TDRE flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Initialization Start transmission [1] Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 12.5 Sample Serial Transmission Flowchart Rev.3.00 Mar. 26, 2007 Page 438 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Rev.3.00 Mar. 26, 2007 Page 439 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.3.00 Mar. 26, 2007 Page 440 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Serial data reception (asynchronous mode): Figure 12.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. No [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After Yes performing the appropriate error PER FER ORER = 1? processing, ensure that the [3] ORER, PER, and FER flags are No all cleared to 0. Reception cannot Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be [4] Read RDRF flag in SSR detected by reading the value of the input port corresponding to the RxD pin. Read ORER, PER, and FER flags in SSR RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC* is activated by an RXI interrupt and the RDR value is read. Note: * The case, in which the DTC automatically clears the RDRF flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the RDRF flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Figure 12.7 Sample Serial Reception Data Flowchart Rev.3.00 Mar. 26, 2007 Page 441 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) [3] Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes No Break? Yes Framing error processing Clear RE bit in SCR to 0 No PER = 1? Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.7 Sample Serial Reception Data Flowchart (cont) Rev.3.00 Mar. 26, 2007 Page 442 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 12.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Rev.3.00 Mar. 26, 2007 Page 443 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition When the next data reception is completed while the RDRF flag in SSR is set to 1 When the stop bit is 0 When the received data differs from the parity (even or odd) set in SMR Data Transfer Receive data is not transferred from RSR to RDR. Receive data is transferred from RSR to RDR. Receive data is transferred from RSR to RDR. Framing error Parity error FER PER Figure 12.8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 12.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev.3.00 Mar. 26, 2007 Page 444 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 12.9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 12.10. Rev.3.00 Mar. 26, 2007 Page 445 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Clock See the section on asynchronous mode. Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 12.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations Multiprocessor serial data transmission: Figure 12.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Rev.3.00 Mar. 26, 2007 Page 446 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC* is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Note: * The case, in which the DTC automatically clears the TDRE flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the TDRE flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart Rev.3.00 Mar. 26, 2007 Page 447 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. Rev.3.00 Mar. 26, 2007 Page 448 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Figure 12.11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop sor bit bit 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor serial data reception: Figure 12.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Rev.3.00 Mar. 26, 2007 Page 449 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR FER ORER = 1? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER ORER = 1? No Read RDRF flag in SSR Yes [4] No RDRF = 1? Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 12.12 Sample Multiprocessor Serial Reception Flowchart Rev.3.00 Mar. 26, 2007 Page 450 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) [5] Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 12.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.3.00 Mar. 26, 2007 Page 451 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Figure 12.13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 ID2 Data2 MPIE bit set to 1 again MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine (b) Data matches station's ID Figure 12.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.3.00 Mar. 26, 2007 Page 452 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB MSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 12.14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Rev.3.00 Mar. 26, 2007 Page 453 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Data Transfer Operations SCI initialization (clocked synchronous mode): Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 12.15 shows a sample SCI initialization flowchart. Rev.3.00 Mar. 26, 2007 Page 454 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. [1] Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 12.15 Sample SCI Initialization Flowchart Rev.3.00 Mar. 26, 2007 Page 455 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Serial data transmission (clocked synchronous mode): Figure 12.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC* is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. Note: * The case, in which the DTC automatically clears the TDRE flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the TDRE flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Initialization Start transmission [1] Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes Clear TE bit in SCR to 0 Figure 12.16 Sample Serial Transmission Flowchart Rev.3.00 Mar. 26, 2007 Page 456 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 12.17 shows an example of SCI operation in transmission. Rev.3.00 Mar. 26, 2007 Page 457 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt request generated request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TEI interrupt request generated Figure 12.17 Example of SCI Operation in Transmission Serial data reception (clocked synchronous mode): Figure 12.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Rev.3.00 Mar. 26, 2007 Page 458 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1? No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC* is activated by a receive data full interrupt (RXI) request and the RDR value is read. Note: * The case, in which the DTC automatically clears the RDRF flag, occurs only when DISEL in DTC is 0 with the transfer counter not being 0. Therefore, the RDRF flag should be cleared by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0. Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 12.18 Sample Serial Reception Flowchart Rev.3.00 Mar. 26, 2007 Page 459 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 12.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 12.19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.19 Example of SCI Operation in Reception Simultaneous serial data transmission and reception (clocked synchronous mode): Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Rev.3.00 Mar. 26, 2007 Page 460 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER = 1? No If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Also, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC* is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Notes: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. * The case, in which the DTC automatically clears the TDRE flag or RDRF flag, occurs only when DISEL in the corresponding DTC transfer is 0 with the transfer counter not being 0. Therefore, the corresponding flag should be cleared by CPU when DISEL in the corresponding DTC transfer is 1, or when DISEL is 0 with the transfer counter being 0. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.3.00 Mar. 26, 2007 Page 461 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 12.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC*. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC*. The DTC cannot be activated by an ERI interrupt request. Note: * The flag is not cleared when DISEL is 0 and the transfer counter value is not 0. Rev.3.00 Mar. 26, 2007 Page 462 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Table 12.12 SCI Interrupt Sources Channel 0 Interrupt Source ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Note: * Description Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Priority* High Low This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of ICR. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. Rev.3.00 Mar. 26, 2007 Page 463 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 12.5 Usage Notes The following points should be noted when using the SCI. Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 18, Power-Down Modes. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 12.13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 12.13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer RSR to RDR X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error Legend: : Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. Rev.3.00 Mar. 26, 2007 Page 464 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Break Detection and Processing (Asynchronous Mode Only) When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only) The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 12.21. Rev.3.00 Mar. 26, 2007 Page 465 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 - Where M: N: D: L: F: 1 2N ) - (L - 0.5) F - | D - 0.5 | N (1 + F) | x 100% ... Formula (1) Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 - 1 2 x 16 ) x 100% ... Formula (2) = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Rev.3.00 Mar. 26, 2007 Page 466 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Restrictions Concerning DTC Updating * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the CPU and DTC. Misoperation may occur if the transmit clock is input within 4 clocks after TDR is updated. (Figure 12.22) * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). * The flag is cleared only when DISEL in DTC is 0 with the transfer counter not being 0. When DISEL is 1,or DISEL is 0 with the transfer counter being 0, the flag should be cleared by CPU. Note that transmitting, in particular, may not successfully be executed unless the TDRE flag is cleared by CPU. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t >4 clocks. Figure 12.22 Example of Clocked Synchronous Transmission by DTC Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read TDR write TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 12.23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 12.24 and 12.25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode Rev.3.00 Mar. 26, 2007 Page 467 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. All data transmitted? Yes Read TEND flag in SSR No [1] [1] TEND = 1? Yes TE = 0 [2] No Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. If TIE and TEIE are set to 1, clear them to 0 in the same way. Includes module stop mode. [2] Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [3] [3] No TE = 1 Figure 12.23 Sample Flowchart for Mode Transition during Transmission Rev.3.00 Mar. 26, 2007 Page 468 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 12.24 Asynchronous Transmission Using Internal Clock Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 12.25 Synchronous Transmission Using Internal Clock Rev.3.00 Mar. 26, 2007 Page 469 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 12.26 shows a sample flowchart for mode transition during reception. RDRF = 1? Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [2] [2] Includes module stop mode. No RE = 1 Figure 12.26 Sample Flowchart for Mode Transition during Reception Rev.3.00 Mar. 26, 2007 Page 470 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) Switching from SCK Pin Function to Port Pin Function * Problem in Operation When switching the SCK pin function to the output port function (high-level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0... Switchover to port output 4. Occurrence of low-level output Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 4. Low-level output 3. C/A = 0 Figure 12.27 Operation when Switching from SCK Pin Function to Port Pin Function Rev.3.00 Mar. 26, 2007 Page 471 of 772 REJ09B0355-0300 Section 12 Serial Communication Interface (SCI) * Sample Procedure for Avoiding Low-Level Output As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0... Switchover to port output 5. CKE1 bit = 0 High-level output SCK/port 1. End of transmission Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 12.28 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev.3.00 Mar. 26, 2007 Page 472 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Section 13 Smart Card Interface 13.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 13.1.1 Features Features of the Smart Card interface supported by the H8S/2245 are as follows. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC) to execute data transfer Rev.3.00 Mar. 26, 2007 Page 473 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Legend: SCMR : Smart Card mode register RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register Figure 13.1 Block Diagram of Smart Card Interface Rev.3.00 Mar. 26, 2007 Page 474 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.1.3 Pin Configuration Table 13.1 shows the Smart Card interface pin configuration. Table 13.1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output 13.1.4 Register Configuration Table 13.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 12, Serial Communication Interface (SCI). Rev.3.00 Mar. 26, 2007 Page 475 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Table 13.2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C 1 Module stop control register MSTPCR Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 476 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 13.2.1 Bit Smart Card Mode Register (SCMR) : 7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : 1 -- SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 13.3.4, Register Settings. Rev.3.00 Mar. 26, 2007 Page 477 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) 13.2.2 Bit Serial Status Register (SSR) : 7 TDRE 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W Note: * : 1 R/(W)* Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5--Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR). Rev.3.00 Mar. 26, 2007 Page 478 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Bit 4--Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description [Clearing conditions] * * 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Bits 3 to 0--Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * * * When 0 is written to TDRE after reading TDRE = 1 When the DTC* is activated by a TXI interrupt and write data to TDR Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 12.5 etu after transmission of a 1-byte serial character when GM = 0 When TDRE = 1 and ERS = 0 (normal transmission) 11.0 etu after transmission of a 1-byte serial character when GM = 1 (Initial value) [Setting conditions] Notes: etu: Elementary Time Unit (time for transfer of 1 bit) * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 479 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.2.3 Bit Serial Mode Register (SMR) : 7 GM 6 CHR 0 0 R/W 5 PE 0 1 R/W 4 O/E 0 O/E R/W 3 STOP 0 1 R/W 2 MP 0 0 R/W 1 CKS1 0 CKS1 R/W 0 CKS0 0 CKS0 R/W Initial value : Set value* : R/W Note: * : 0 GM R/W When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. The function of bit 7 of SMR changes in smart card interface mode. Bit 7--GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation * * 1 * * TEND flag generation 12.5 etu after beginning of start bit Clock output ON/OFF control only TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) (Initial value) GSM mode smart card interface mode operation Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0--Operate in the same way as for the normal SCI. For details, see section 12.2.5, Serial Mode Register (SMR). Rev.3.00 Mar. 26, 2007 Page 480 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.2.4 Bit Serial Control Register (SCR) : 7 TIE 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : 0 R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2--Operate in the same way as for the normal SCI. For details, see section 12.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. SCMR SMIF 0 1 1 1 1 1 1 SMR C/A, GM A See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCR Setting CKE1 CKE0 SCK Pin Function Rev.3.00 Mar. 26, 2007 Page 481 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.3 13.3.1 Operation Overview The main functions of the Smart Card interface are as follows. * One frame consists of 8-bit data plus a parity bit. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no clocked synchronous communication function. Rev.3.00 Mar. 26, 2007 Page 482 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.3.2 Pin Connections Figure 13.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. VCC TxD I/O RxD SCK Rx (port) H8S/2245 Connected equipment Data line Clock line Reset line CLK RST IC card Figure 13.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev.3.00 Mar. 26, 2007 Page 483 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.3.3 Data Format Figure 13.3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output : Start bit : Data bits : Parity bit : Error signal Legend: Ds D0 to D7 Dp DE Figure 13.3 Smart Card Interface Data Format Rev.3.00 Mar. 26, 2007 Page 484 of 772 REJ09B0355-0300 Section 13 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. 13.3.4 Register Settings Table 13.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Rev.3.00 Mar. 26, 2007 Page 485 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Table 13.3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Legend: -- : Unused bit Note: * The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 13.3.5, Clock. BRR Setting BRR is used to set the bit rate. See section 13.3.5, Clock, for the method of calculating the value to be set. SCR Setting The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 12, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Rev.3.00 Mar. 26, 2007 Page 486 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Smart Card Mode Register (SCMR) Setting The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). * Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. * Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2245 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). Rev.3.00 Mar. 26, 2007 Page 487 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 13.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= 1488 x 2 2n-1 x (N + 1) x 10 6 Where N = Value set in BRR (0 N 255) B = Bit rate (bit/s) = Operating frequency (MHz) n = See table 13.4 Table 13.4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Table 13.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 Note: Bit rates are rounded to the nearest whole number. Rev.3.00 Mar. 26, 2007 Page 488 of 772 REJ09B0355-0300 Section 13 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 N 255, and the smaller error is specified. N= 1488 x 2 2n-1 xB x 10 - 1 6 Table 13.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0) (MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 N Error 6.60 N Error N Error N Error 1 30 1 25 1 8.99 N Error N Error N Error 1 0.00 1 12.01 2 15.99 2 Table 13.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( 1488 x 2 2n-1 x B x (N + 1) x 10 - 1) x 100 6 Rev.3.00 Mar. 26, 2007 Page 489 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 13.3.6 Data Transfer Operations Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev.3.00 Mar. 26, 2007 Page 490 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Serial Data Transmission As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 13.4 shows a flowchart for transmitting, and figure 13.5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 13.6. If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DTC below. Rev.3.00 Mar. 26, 2007 Page 491 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 13.4 Example of Transmission Processing Flow Rev.3.00 Mar. 26, 2007 Page 492 of 772 REJ09B0355-0300 Section 13 Smart Card Interface TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 13.5 Relation Between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 1 11.0etu Legend: Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal Figure 13.6 TEND Flag Generation Timing in Transmission Operation Rev.3.00 Mar. 26, 2007 Page 493 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Serial Data Reception Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 13.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0? Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 13.7 Example of Reception Processing Flow With the above processing, interrupt servicing or data transfer by the or DTC is possible. Rev.3.00 Mar. 26, 2007 Page 494 of 772 REJ09B0355-0300 Section 13 Smart Card Interface If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 13.8 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 13.8 Timing for Fixing Clock Output Level Rev.3.00 Mar. 26, 2007 Page 495 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Interrupt Operation There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 13.8. Table 13.8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DTC Activation Possible Not possible Possible Not possible Data Transfer Operation by DTC In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. When DISEL in DTC is 0 and the transfer counter value is not 0, the TDRE and TEND flags are automatically cleared to 0 when data transfer is performed. If DISEL is 1, or if DISEL is 0 and the transfer counter value is 0, the DTC writes the transfer data to TDR but does not clear the flags. Therefore, the flags should be cleared by the CPU. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DTC is not activated. Thus, the number of bytes specified by the SCI and DTC are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. Rev.3.00 Mar. 26, 2007 Page 496 of 772 REJ09B0355-0300 Section 13 Smart Card Interface When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 7, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and transfer of the receive data will be carried out. At this time, the RDRF flag is cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0. If DISEL is 1, or if DISEL is 0 and the transfer counter value is 0, the DTC transfers the receive data but does not clear the flag. Therefore, the flag should be cleared by the CPU. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 13.3.7 Operation in GSM Mode Switching the Mode When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. * When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state. * When returning to smart card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty. Rev.3.00 Mar. 26, 2007 Page 497 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Normal operation Software standby Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 13.9 Clock Halt and Restart Procedure Powering On To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 13.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In Smart Card Interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 13.10. Rev.3.00 Mar. 26, 2007 Page 498 of 772 REJ09B0355-0300 Section 13 Smart Card Interface 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.10 Receive Data Sampling Timing in Smart Card Mode Thus the reception margin in asynchronous mode is given by the following formula. M = | (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | N (1 + F) | x 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev.3.00 Mar. 26, 2007 Page 499 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. * Retransfer operation when SCI is in receive mode Figure 13.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Transfer frame n+1 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 [4] [3] Figure 13.11 Retransfer Operation in SCI Receive Mode Rev.3.00 Mar. 26, 2007 Page 500 of 772 REJ09B0355-0300 Section 13 Smart Card Interface * Retransfer operation when SCI is in transmit mode Figure 13.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] [8] [9] Transfer to TSR from TDR Transfer to TSR from TDR Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 Figure 13.12 Retransfer Operation in SCI Transmit Mode Rev.3.00 Mar. 26, 2007 Page 501 of 772 REJ09B0355-0300 Section 13 Smart Card Interface Rev.3.00 Mar. 26, 2007 Page 502 of 772 REJ09B0355-0300 Section 14 A/D Converter Section 14 A/D Converter 14.1 Overview The H8/2245 Group incorporates a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. 14.1.1 Features A/D converter features are listed below * 10-bit resolution * Four input channels * Settable analog conversion voltage range Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage * High-speed conversion Minimum conversion time: 6.5 s per channel (at 20-MHz operation) * Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin * A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion * Module stop mode can be set As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Continuous A/D conversion on 1 to 4 channels Rev.3.00 Mar. 26, 2007 Page 503 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the A/D converter. Module data bus Internal data bus AVCC Vref AVSS 10-bit D/A Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 AN1 AN2 AN3 + Multiplexer - Comparator Sample-andhold circuit Control circuit Bus interface /8 /16 ADI interrupt Conversion start trigger from 8-bit timer or TPU ADTRG Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 14.1 Block Diagram of A/D Converter Rev.3.00 Mar. 26, 2007 Page 504 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.1.3 Pin Configuration Table 14.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. Table 14.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 I/O Input Input Input Input Input Input Input Input Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 External trigger input for starting A/D conversion A/D external trigger input pin ADTRG Rev.3.00 Mar. 26, 2007 Page 505 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.1.4 Register Configuration Table 14.2 summarizes the registers of the A/D converter. Table 14.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR R/W R R R R R R R R R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF Address* H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C 1 Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 506 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.2 14.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 14.3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 14.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 14.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel AN0 AN1 AN2 AN3 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.3.00 Mar. 26, 2007 Page 507 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 -- 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] * * 1 * * Note: * When 0 is written to the ADF flag after reading ADF = 1 When the DTC* is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels (Initial value) [Setting conditions] The flag is cleared only when DISEL in DTC is 0 and the transfer counter value is not 0. Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 508 of 772 REJ09B0355-0300 Section 14 A/D Converter Bit 5--A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description * * * A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 14.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0). Set the conversion time to a value equal to or greater than the conversion time indicated in section 19.5, A/D Conversion Characteristics. Bit 3 CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Bit 2--Reserved: This bit can be read or written, but should only be written with 0. Rev.3.00 Mar. 26, 2007 Page 509 of 772 REJ09B0355-0300 Section 14 A/D Converter Bits 1 and 0--Channel Select 1 and 0 (CH1, CH0): Together with the SCAN bit, these bits select the analog input channel(s). Only set the input channel while conversion is stopped. Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 Description Single Mode (SCAN = 0) AN0 AN1 AN2 AN3 (Initial value) Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 14.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in hardware standby mode or module stop mode. Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped. Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description Start of A/D conversion by external trigger is disabled Start of A/D conversion by external trigger (TPU) is enabled Start of A/D conversion by external trigger (8-bit timer) is enabled Start of A/D conversion by external trigger pin is enabled (Initial value) Bits 5 to 0--Reserved: These bits are reserved; they are always read as 1 and cannot be modified. Rev.3.00 Mar. 26, 2007 Page 510 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 18.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9--Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) Rev.3.00 Mar. 26, 2007 Page 511 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 14.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 14.2 ADDR Access Operation (Reading H'AA40) Rev.3.00 Mar. 26, 2007 Page 512 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 14.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Rev.3.00 Mar. 26, 2007 Page 513 of 772 REJ09B0355-0300 Section 14 A/D Converter Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result* A/D conversion result 1 Read conversion result* A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev.3.00 Mar. 26, 2007 Page 514 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 14.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev.3.00 Mar. 26, 2007 Page 515 of 772 REJ09B0355-0300 Section 14 A/D Converter Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev.3.00 Mar. 26, 2007 Page 516 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D conversion timing. Table 14.4 indicates the A/D conversion time. As indicated in figure 14.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14.4. In scan mode, the values given in table 14.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1) : (2) : tD : tSPL : tCONV : ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 14.5 A/D Conversion Timing Rev.3.00 Mar. 26, 2007 Page 517 of 772 REJ09B0355-0300 Section 14 A/D Converter Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 10 -- 259 Typ -- 63 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 31 -- Max 9 -- 134 Note: Values in the table are the number of states. 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 14.6 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 14.6 External Trigger Input Timing Rev.3.00 Mar. 26, 2007 Page 518 of 772 REJ09B0355-0300 Section 14 A/D Converter 14.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 14.5. Table 14.5 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible 14.6 Usage Notes The following points should be noted when using the A/D converter. Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, see section 18, Power-Down Modes. Setting Range of Analog Power Supply and Other Pins (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN3 during A/D conversion should be in the range AVSS ANn AVref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref AVCC. Note: If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Rev.3.00 Mar. 26, 2007 Page 519 of 772 REJ09B0355-0300 Section 14 A/D Converter Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN3), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN3) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 14.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN3 must be connected to AVSS. If a filter capacitor is connected as shown in figure 14.7, the input currents at the analog input pins (AN0 to AN3) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Rev.3.00 Mar. 26, 2007 Page 520 of 772 REJ09B0355-0300 Section 14 A/D Converter AVCC Vref Rin*2 *1 *1 0.1 F AVSS 100 AN0 to AN3 Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 14.7 Example of Analog Input Protection Circuit Table 14.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Note: * Min -- -- Max 20 10* Unit pF k When VCC = 4.0 V to 5.5 V and 12 MHz 10 k AN0 to AN3 To A/D converter 20 pF Note: Values are reference values. Figure 14.8 Analog Input Pin Equivalent Circuit Rev.3.00 Mar. 26, 2007 Page 521 of 772 REJ09B0355-0300 Section 14 A/D Converter A/D Conversion Precision Definitions H8S/2245 Group A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 14.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 14.10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev.3.00 Mar. 26, 2007 Page 522 of 772 REJ09B0355-0300 Section 14 A/D Converter Digital output H'3FF H'3FE Ideal A/D conversion characteristic Quantization error H'001 H'000 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 14.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 14.10 A/D Conversion Precision Definitions (2) Rev.3.00 Mar. 26, 2007 Page 523 of 772 REJ09B0355-0300 Section 14 A/D Converter Permissible Signal Source Impedance H8S/2245 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/sec or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8/2245 Group Sensor output impedance Up to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Note: Values are reference values. Figure 14.11 Example of Analog Input Circuit Rev.3.00 Mar. 26, 2007 Page 524 of 772 REJ09B0355-0300 Section 15 RAM Section 15 RAM 15.1 Overview The H8S/2246, H8S/2244, and H8S/2242 have 8 kbytes of on-chip high-speed static RAM, and the H8S/2245, H8S/2243, H8S/2241, and H8S/2240 have 4 kbytes. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. The on-chip RAM on the H8S/2246, H8S/2244, and H8S/2242 is located in addresses H'E400 to H'FBFF (6 kbytes) in normal mode (modes 1 to 3), and in addresses H'FFDC00 to H'FFFBFF (8 kbytes) in advanced mode (modes 4 to 7). The on-chip RAM on the H8S/2245, H8S/2243, H8S/2241, and H8S/2240 is located in addresses H'EC00 to H'FBFF (4 kbytes) in normal mode (modes 1 to 3), and in addresses H'FFEC00 to H'FFFBFF (4 kbytes) in advanced mode (modes 4 to 7). The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). Rev.3.00 Mar. 26, 2007 Page 525 of 772 REJ09B0355-0300 Section 15 RAM 15.1.1 Block Diagram Figure 15.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFDC00 H'FFDC02 H'FFDC04 H'FFDC01 H'FFDC03 H'FFDC05 H'FFFBFE H'FFFBFF Figure 15.1 Block Diagram of RAM (Example with H8S/2246 in Advanced Mode) 15.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 15.1 shows the register configuration. Table 15.1 Register Configuration Name System control register Note: * Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FF39 Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 526 of 772 REJ09B0355-0300 Section 15 RAM 15.2 15.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 -- 0 RAME 1 R/W Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: Do not clear the RAME bit to 0 when the DTC is used. 15.3 Operation When the RAME bit is set to 1, accesses to H8S/2246, H8S/2244, and H8S/2242 addresses H'FFDC00 to H'FFFBFF, and H8S/2245, H8S/2243, H8S/2241, and H8S/2240 addresses H'FFEC00 to H'FFFBFF, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. Rev.3.00 Mar. 26, 2007 Page 527 of 772 REJ09B0355-0300 Section 15 RAM Rev.3.00 Mar. 26, 2007 Page 528 of 772 REJ09B0355-0300 Section 16 ROM Section 16 ROM 16.1 Overview The H8S/2246 and H8S/2245 have 128 kbytes of on-chip ROM (PROM or mask ROM). The H8S/2244 and H8S/2243 have 64 kbytes of on-chip ROM (mask ROM). The H8S/2242 and H8S/2241 have 32 kbytes of on-chip ROM (mask ROM). The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. The PROM version of the H8S/2245 Group (H8S/2246) can be programmed with a generalpurpose PROM programmer, by setting PROM mode. Rev.3.00 Mar. 26, 2007 Page 529 of 772 REJ09B0355-0300 Section 16 ROM 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'00FFFE H'010000 H'010002 H'00FFFF H'010001 H'010003 When EAE= 0 H'01FFFE H'01FFFF Figure 16.1 Block Diagram of ROM (Example with H8S/2246 and H8S/2245 in Modes 6, 7) 16.1.2 Register Configuration The on-chip ROM is controlled by BCRL. The register configuration is shown in table 16.1. Table 16.1 Register Configuration Initial Value Name Bus control register L Note: * Abbreviation BCRL R/W R/W Power-On Reset H'3C Manual Reset Retained Address* H'FED5 Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 530 of 772 REJ09B0355-0300 Section 16 ROM 16.2 16.2.1 Bit Register Descriptions Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 -- 1 R/W 3 -- 1 R/W 2 ASS 1 R/W 1 -- 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus release state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Enabling or disabling of part of the on-chip ROM area can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL). Bit 5--External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode. Bit 5 EAE 0 Description Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2246 and H8S/2245) or a reserved area* (in the H8S/2244, H8S/2243, H8S/2242, and H8S/2241). Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode). (Initial value) * Reserved areas should not be accessed. 1 Note: Rev.3.00 Mar. 26, 2007 Page 531 of 772 REJ09B0355-0300 Section 16 ROM 16.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. These settings are shown in table 16.2. In the H8S/2246, H8S/2245, H8S/2244, and H8S/2243 normal mode, a maximum of 56 kbytes of ROM can be used. Table 16.2 Operating Modes and ROM Area Mode Pin Setting Operating Mode Mode 1 Normal expanded mode with on-chip ROM disabled Normal expanded mode with on-chip ROM enabled Normal single-chip mode Advanced expanded 1 mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 0 MD2 0 MD1 0 MD0 1 BCRL EAE -- On-Chip ROM H8S/2246 and H8S/2244 and H8S/2242 and H8S/2245 H8S/2243 H8S/2241 Disabled Disabled Disabled Mode 2 1 0 -- Enabled (56 kbytes) Enabled (56 kbytes) Enabled (32 kbytes) Mode 3 Mode 4 1 0 -- Disabled Disabled Disabled Mode 5 1 Mode 6 0 0 1 Enabled (128 kbytes) Enabled (64 kbytes) Enabled (128 kbytes) Enabled (64 kbytes) Enabled (64 kbytes) Enabled (32 kbytes) Mode 7 1 0 1 In H8S/2246 and H8S/2245 modes 6 and 7, the on-chip ROM available after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Rev.3.00 Mar. 26, 2007 Page 532 of 772 REJ09B0355-0300 Section 16 ROM 16.4 16.4.1 PROM Mode PROM Mode Setting The PROM version of the H8S/2245 Group suspends its microcontroller functions when placed in PROM mode, enabling the on-chip PROM to be programmed. This programming can be done with a PROM programmer set up in the same way as for the HN27C101 EPROM (VPP = 12.5 V). Use of a 100-pin/32-pin socket adapter enables programming with a commercial PROM programmer. Note that the PROM programmer should not be set to page mode as the H8S/2245 Group does not support page programming. Table 16.3 shows how PROM mode is selected. Table 16.3 Selecting PROM Mode Pin Names MD2, MD1, MD0 STBY PA2, PA1 High Setting Low 16.4.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a 100-pin/32-pin socket adapter to the PROM programmer. Table 16.4 gives ordering information for the socket adapter, and figure 16.2 shows the wiring of the socket adapter. Figure 16.3 shows the memory map in PROM mode. Rev.3.00 Mar. 26, 2007 Page 533 of 772 REJ09B0355-0300 Section 16 ROM H8S/2245 Group FP-100B, TFP-100B 62 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 41 63 43 44 45 46 47 48 50 74 42 75 40, 65, 98 77 78 51 52 7, 18, 31 49, 68, 84 83 64 57 58 61 AVSS STBY MD0 MD1 MD2 Legend: VPP Pin RES PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 NMI PB2 PB3 PB4 PB5 PB6 PB7 PA0 PF2 PB1 PF1 VCC AVCC Vref PA1 PA2 VSS EPROM socket Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC HN27C101 (32 Pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 VSS 16 Note: Pins not shown in this figure should be left open. : Programming power supply (12.5 V) EO7 to EO0 : Data input/output EA16 to EA0 : Address input : Output enable OE : Chip enable CE : Program PGM Figure 16.2 Wiring of 100-Pin/32-Pin Socket Adapter Rev.3.00 Mar. 26, 2007 Page 534 of 772 REJ09B0355-0300 Section 16 ROM Table 16.4 Socket Adapter Microcontroller H8S/2246 Package 100 pin QFP (FP-100B) 100 pin TQFP (TFP-100B) Socket Adapter HS2245ESHS1H HS2245ESNS1H Addresses in MCU mode H'000000 Addresses in PROM mode H'00000 On-chip PROM H'01FFFF H'1FFFF Figure 16.3 Memory Map in PROM Mode Rev.3.00 Mar. 26, 2007 Page 535 of 772 REJ09B0355-0300 Section 16 ROM 16.5 16.5.1 Programming Overview Table 16.5 shows how to select the program, verify, and program-inhibit modes in PROM mode. Table 16.5 Mode Selection in PROM Mode Pins Mode Program Verify Program-inhibit CE L L L L H H Legend: L: Low voltage level H: High voltage level VPP: VPP voltage level VCC: VCC voltage level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input Programming and verification should be carried out using the same specifications as for the standard HN27C101 EPROM. However, do not set the PROM programmer to page mode does not support page programming. A PROM programmer that only supports page programming cannot be used. When choosing a PROM programmer, check that it supports high-speed programming in byte units. Always set addresses within the range H'00000 to H'1FFFF. 16.5.2 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 16.4 shows the basic high-speed programming flowchart. Tables 16.6 and 16.7 list the electrical characteristics of the chip during programming. Figure 16.5 shows a timing chart. Rev.3.00 Mar. 26, 2007 Page 536 of 772 REJ09B0355-0300 Section 16 ROM Start Set programming/ verification mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n + 1 n Yes No n < 25? Program with tPW = 0.2 ms 5% Address + 1 address No Verification OK? Yes Program with tOPW = 0.2n ms No Last address? Yes Set read mode VCC = 5.0 V 0.25 V VPP = VCC Fail No go All addresses read? Go End Figure 16.4 High-Speed Programming Flowchart Rev.3.00 Mar. 26, 2007 Page 537 of 772 REJ09B0355-0300 Section 16 ROM Table 16.6 DC Characteristics in PROM Mode When VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C Item Input high voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM EO7 to EO0, EA16 to EA0, OE, CE, PGM EO7 to EO0 EO7 to EO0, EA16 to EA0, OE, CE, PGM Symbol Min VIH 2.4 Typ -- Max VCC +0.3 (Preliminary) Test Unit Conditions V Input low voltage VIL -0.3 -- 0.8 V Output high voltage EO7 to EO0 Output low voltage Input leakage current VCC current VPP current VOH VOL | IIL | 2.4 -- -- -- -- -- -- 0.45 2 V V A IOH = -200 A IOL = 1.6 mA Vin = 5.25 V/0.5 V ICC IPP -- -- -- -- 40 40 mA mA Rev.3.00 Mar. 26, 2007 Page 538 of 772 REJ09B0355-0300 Section 16 ROM Table 16.7 AC Characteristics in PROM Mode When VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width Symbol tAS tOES tDS tAH tDH tDF* tVPS tPW 3 2 (Preliminary) Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 150 Unit s s s s s ns s ms ms s s ns Test Conditions Figure 16.5* 1 PGM pulse width for overwrite programming tOPW* VCC setup time CE setup time Data output delay time tVCS tCES tOE Notes: 1. Input pulse level: 0.8 V to 2.2 V Input rise time and fall time 20 ns Timing reference levels; Input: 1.0 V, 2.0 V; Output: 0.8 V, 2.0 V 2. tDF is defined to be when output has reached the open state, and the output level can no longer be referenced. 3. tOPW is defined by the value shown in the flowchart. Rev.3.00 Mar. 26, 2007 Page 539 of 772 REJ09B0355-0300 Section 16 ROM Program Address tAS Data tDS VPP VCC VPP VCC VCC+1 VCC tVCS tVPS Input data tDH Verify tAH Output data tDF CE tCES PGM tPW OE tOPW* tOES tOE Note: * tOPW is defined by the value shown in the flowchart. Figure 16.5 PROM Programming/Verification Timing Rev.3.00 Mar. 26, 2007 Page 540 of 772 REJ09B0355-0300 Section 16 ROM 16.5.3 Programming Precautions * Program using the specified voltages and timing. The programming voltage (VPP) in PROM mode is 12.5 V. If the PROM programmer is set to Renesas Technology HN27C101 specifications, VPP will be 12.5 V. Applied voltages in excess of the specified values can permanently destroy the MCU. Be particularly careful about the PROM programmer's overshoot characteristics. * Before programming, check that the MCU is correctly mounted in the PROM programmer. Overcurrent damage to the MCU can result if the index marks on the PROM programmer, socket adapter, and MCU are not correctly aligned. * Do not touch the socket adapter or MCU while programming. Touching either of these can cause contact faults and programming errors. * The MCU cannot be programmed in page programming mode. Select the programming mode carefully. * The size of the PROM is 128 kbytes. Always set addresses within the range H'00000 to H'1FFFF. During programming, write H'FF to unused addresses to avoid verification errors. Rev.3.00 Mar. 26, 2007 Page 541 of 772 REJ09B0355-0300 Section 16 ROM 16.5.4 Reliability of Programmed Data An effective way to assure the data retention characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM cells prone to early failure. Figure 16.6 shows the recommended screening procedure. Program chip and verify data Bake chip for 24 to 48 hours at 125C to 150C with power off Read and check program Mount Figure 16.6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is being used, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. Rev.3.00 Mar. 26, 2007 Page 542 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator Section 17 Clock Pulse Generator 17.1 Overview The H8S/2245 Group has a built-in clock pulse generator (CPG) that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit. 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the clock pulse generator. SCKCR SCK2 to SCK0 Mediumspeed divider EXTAL Oscillator circuit XTAL Duty adjustment circuit /2 to /32 Bus master clock selection circuit System clock to pin Internal clock to supporting modules Bus master clock to CPU and DTC Figure 17.1 Block Diagram of Clock Pulse Generator Rev.3.00 Mar. 26, 2007 Page 543 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator 17.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWCR. Table 17.1 shows the register configuration. Table 17.1 Clock Pulse Generator Register Name System clock control register Low power control register Note: * Abbreviation SCKCR LPWCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FF3A H'FF44 Lower 16 bits of the address. 17.2 17.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value: R/W : SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Output Disable (PSTOP): Controls output. Description Bit 7 PSTOP 0 1 Normal Operation output (initial value) Fixed high Sleep Mode output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Rev.3.00 Mar. 26, 2007 Page 544 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator Bit 6--Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 -- Description Bus master is in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value) 17.2.2 Bit Low Power Control Register (LPWCR) : 7 -- 0 R/W 6 -- 0 R/W 5 RFCUT 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W Initial value: R/W : LPWCR is an 8-bit readable/writable register that controls the oscillator's built-in feedback resistor when using external clock input. LPWCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 6 and 7--Reserved: These bits can be read or written to, but do not affect operation. Bit 5--Built-in Feedback Resistor Control (RFCUT): Selects whether the oscillator's built-in feedback resistor and duty adjustment circuit are used with external clock input. Do not access this bit when a crystal oscillator is used. When an external clock is input, a temporary transition should be made to software standby mode after setting this bit. When software standby mode is entered, it is possible to select use or non-use Rev.3.00 Mar. 26, 2007 Page 545 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator of the oscillator's built-in feedback resistor and duty adjustment circuit. Software standby mode should then be exited by means of an external interrupt. Bit 5 RFCUT 0 1 Description Oscillator's built-in feedback resistor and duty adjustment circuit are used (Initial value) Oscillator's built-in feedback resistor and duty adjustment circuit are not used Bits 4 to 0--Reserved: These bits can be read or written to, but do not affect operation. 17.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 17.3.1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as shown in the example in figure 17.2. Select the damping resistance Rd according to table 17.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 17.2 Connection of Crystal Resonator (Example) Table 17.2 Damping Resistance Value Frequency (MHz) Rd () 2 1k 4 500 8 200 12 0 16 0 20 0 Rev.3.00 Mar. 26, 2007 Page 546 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator Crystal resonator Figure 17.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 17.3 and the same resonance frequency as the system clock (). CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 17.3 Crystal Resonator Equivalent Circuit Table 17.3 Crystal Resonator Parameters Frequency (MHz) Rs max () C0 max (pF) 2 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 Note on Board Design When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 17.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 Signal A Signal B H8S/2245 XTAL EXTAL CL1 Figure 17.4 Example of Incorrect Board Design Rev.3.00 Mar. 26, 2007 Page 547 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator 17.3.2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in figure 17.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 17.5 External Clock Input (Examples) Rev.3.00 Mar. 26, 2007 Page 548 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator External Clock The external clock signal should have the same frequency as the system clock (). Table 17.4 and figure 17.6 show the input conditions for the external clock. Table 17.4 External Clock Input Conditions VCC = 2.7 V to 5.5 V Item External clock input pulse width low level External clock input pulse width high level External clock rise time External clock fall time Clock pulse width low level Clock pulse width high level Note: * Symbol tEXL Min 40 Max -- VCC = 2.7 V to 5.5 V* Min 30 Max -- VCC = 5.0 V 10% Min 20 Max -- Unit ns Test Conditions Figure 17.6 tEXH 40 -- 30 -- 20 -- ns tEXr tEXf tCL tCH -- -- 0.4 80 0.4 80 10 10 0.6 -- 0.6 -- -- -- 0.4 80 0.4 80 7.5 7.5 0.6 -- 0.6 -- -- -- 0.4 80 0.4 80 5 5 0.6 -- 0.6 -- ns ns tcyc ns tcyc ns 5 MHz < 5 MHz 5 MHz < 5 MHz Figure 19.4 Does not apply to the HD6472246. Table 17.5 and figure 17.6 show the external clock input conditions when the duty adjustment circuit is not used. When the duty adjustment circuit is not used, the output waveform depends on the external clock input waveform, and therefore no specifications are provided. Rev.3.00 Mar. 26, 2007 Page 549 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator Table 17.5 External Clock Input Conditions when Duty Adjustment Circuit Is Not Used VCC = 2.7 V to 5.5 V Item External clock input pulse width low level External clock input pulse width high level External clock rise time External clock fall time Symbol tEXL Min 50 Max -- VCC = 2.7 V to 5.5 V* Min 37.5 Max -- VCC = 5.0 V 10% Min 25 Max -- Unit ns Test Conditions Figure 17.6 tEXH 50 -- 37.5 -- 25 -- ns tEXr tEXf -- -- 10 10 -- -- 7.5 7.5 -- -- 5 5 ns ns Notes: When the duty adjustment circuit is not used, the maximum operating frequency falls according to the input waveform. (Example: When tEXL = tEXH = 25 ns and tEXr = tEXf = 5 ns, the clock cycle time = 60 ns, and therefore the maximum operating frequency = 16.7 MHz.) * Does not apply to the HD6472246. tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 17.6 External Clock Input Timing Rev.3.00 Mar. 26, 2007 Page 550 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator Note on External Clock Switchover When using two or more external clocks (e.g. 10 MHz and 32 kHz), input clock switchover should be carried out in software standby mode. A sample external clock switching circuit is shown in figure 17.7, and sample external clock switchover timing in figure 17.8. H8S/2245 External clock switchover request Port output Control circuit External interrupt signal External clock switchover signal External interrupt Selector External clock 1 External clock 2 EXTAL Figure 17.7 Sample External Clock Switching Circuit Rev.3.00 Mar. 26, 2007 Page 551 of 772 REJ09B0355-0300 External clock 1 External clock 2 Operation (1) Clock switchover request Sleep instruction execution Interrupt exception handling (5) Section 17 Clock Pulse Generator Port setting (2) (3) Rev.3.00 Mar. 26, 2007 Page 552 of 772 REJ09B0355-0300 Standby time 200 ns or more (4) Active (external clock 2) Software standby mode Active (external clock 1) External clock switchover signal EXTAL Internal clock Figure 17.8 Sample External Clock Switchover Timing External interrupt (1) (2) (3) (4) Port setting (clock switchover) Software standby mode transition External clock switchover External interrupt generation (Input interrupt 200 ns or more after transition to software standby mode.) (5) Interrupt exception handling Section 17 Clock Pulse Generator 17.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (). 17.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 17.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock () or one of the medium-speed clocks (/2, /4, /8, /16, and /32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 17.7 Note on Crystal Resonator As various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev.3.00 Mar. 26, 2007 Page 553 of 772 REJ09B0355-0300 Section 17 Clock Pulse Generator Rev.3.00 Mar. 26, 2007 Page 554 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Section 18 Power-Down Modes 18.1 Overview In addition to the normal program execution state, the H8S/2245 Group has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2245 Group operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode Of these, (2) to (6) are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2245 Group is in high-speed mode. Table 18.1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode. Rev.3.00 Mar. 26, 2007 Page 555 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Table 18.1 Operating Modes Operating Transition Clearing Mode Condition Condition High speed Control register mode Mediumspeed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Control register Oscillator Functions Functions High speed Medium speed Halted High/ medium speed Halted CPU Registers Functions Functions High speed High/ medium speed*1 High speed Halted Modules Registers Functions Functions I/O Ports High speed High speed Instruction Interrupt Functions Functions Retained Functions Functions Retained/ reset*2 Retained/ reset*2 Reset High speed Retained Control register Instruction External interrupt Halted Retained Halted Retained Pin Halted Halted Undefined Halted High impedance Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI and A/D are reset, and other on-chip supporting modules retain their state. 18.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 18.2 summarizes these registers. Table 18.2 Power-Down Mode Registers Name Standby control register System clock control register Module stop control register H Module stop control register L Note: * Abbreviation SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'3F H'FF Address* H'FF38 H'FF3A H'FF3C H'FF3D Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 556 of 772 REJ09B0355-0300 Section 18 Power-Down Modes 18.2 18.2.1 Bit Register Descriptions Standby Control Register (SBYCR) : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it. Bit 7 SSBY 0 1 Description Transition to sleep mode after execution of SLEEP instruction (Initial value) Transition to software standby mode after execution of SLEEP instruction Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 18.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made. Rev.3.00 Mar. 26, 2007 Page 557 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Initial value) Bit 3--Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS3, AS, RD, HWR, LWR) is retained or set to the high-impedance state in software standby mode. Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value) Bits 2 to 0--Reserved: Read-only bits, always read as 0. 18.2.2 Bit System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev.3.00 Mar. 26, 2007 Page 558 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Bit 7-- Clock Output Disable (PSTOP): Controls output. Description Bit 7 PSTOP 0 1 Normal Operating Mode output (initial value) Fixed high Sleep Mode output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bits 6--Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value) 18.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. Rev.3.00 Mar. 26, 2007 Page 559 of 772 REJ09B0355-0300 Section 18 Power-Down Modes MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0--Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 18.3 for the method of selecting on-chip supporting modules. Bits 15 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode cleared Module stop mode set 18.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 560 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Figure 18.1 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode , supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 18.1 Medium-Speed Mode Transition and Clearance Timing 18.4 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 561 of 772 REJ09B0355-0300 Section 18 Power-Down Modes 18.5 18.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 18.3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. If a transition is made to sleep mode when all modules are stopped (MSTPCR = H'FFFF) or modules other than the 8-bit timers are stopped (MSTPCR = H'EFFF), operation of the bus controller and I/O ports is also halted, enabling current dissipation to be further reduced. Rev.3.00 Mar. 26, 2007 Page 562 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Table 18.3 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRH Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module -- Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer -- -- A/D converter -- Serial communication interface (SCI) channel 2 Serial communication interface (SCI) channel 1 Serial communication interface (SCI) channel 0 -- -- -- -- -- Note: Bits 15, 11, 10, 8, and 4 to 0 can be read or written to, but do not affect operation. 18.5.2 Usage Notes DTC Module Stop Mode: Depending on the operating status of the DTC, the MSTP14 bit may not be set to 1. Setting of the DTC module stop mode should be carried out only when the DTC is not activated. For details, refer to section 7, Data Transfer Controller. On-Chip Supporting Module Interrupts: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. Rev.3.00 Mar. 26, 2007 Page 563 of 772 REJ09B0355-0300 Section 18 Power-Down Modes 18.6 18.6.1 Software Standby Mode Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 18.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin or STBY pin. Clearing with an Interrupt When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire H8S/2245 Group chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Clearing with the RES Pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2245 Group chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. Clearing with the STBY Pin When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 564 of 772 REJ09B0355-0300 Section 18 Power-Down Modes 18.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 18.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 18.4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz 0.41 0.51 0.68 0.82 1.0 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.4 2.7 5.5 1.6 3.3 6.6 2.0 4.1 8.2 1.4 2.7 5.5 2.0 4.1 4.1 8.2 Unit ms 8.2 16.4 10.9 16.4 32.8 10.9 13.1 16.4 21.8 32.8 65.5 13.1 16.4 21.8 26.2 32.8 43.7 65.5 131.1 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 2.7 -- 4.0 -- 8.0 -- s : Recommended time setting Using an External Clock Any value can be set. Normally, use of the minimum time is recommended. 18.6.4 Software Standby Mode Application Example Figure 18.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Rev.3.00 Mar. 26, 2007 Page 565 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 18.2 Software Standby Mode Application Example 18.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Rev.3.00 Mar. 26, 2007 Page 566 of 772 REJ09B0355-0300 Section 18 Power-Down Modes 18.7 18.7.1 Hardware Standby Mode Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2245 Group is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillation stabilizes (at least tOSC1--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 18.7.2 Hardware Standby Mode Timing Figure 18.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Rev.3.00 Mar. 26, 2007 Page 567 of 772 REJ09B0355-0300 Section 18 Power-Down Modes Oscillator RES STBY Oscillation stabilization time tOSC1 Reset exception handling Figure 18.3 Hardware Standby Mode Timing (Example) 18.8 Clock Output Disabling Function Output of the clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 18.5 shows the state of the pin in each processing mode. Table 18.5 Pin State in Each Processing Mode Register Settings DDR 0 1 1 PSTOP x 0 1 Normal Mode output Fixed high Sleep Mode output Fixed high Software Standby Mode Hardware Standby Mode High impedance High impedance High impedance High impedance Fixed high Fixed high High impedance High impedance Legend: x: Don't care Rev.3.00 Mar. 26, 2007 Page 568 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Section 19 Electrical Characteristics 19.1 Absolute Maximum Ratings Table 19.1 lists the absolute maximum ratings. Table 19.1 Absolute Maximum Ratings Item Power supply voltage Programming voltage Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC VPP Vin Vin Vref AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to +13.5 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature -55 to +125 Unit V V V V V V V C C C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Rev.3.00 Mar. 26, 2007 Page 569 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.2 Power Supply Voltage and Operating Frequency Ranges Power supply voltage and operating frequency ranges (shaded areas) are shown in table 19.2. Table 19.2 Power Supply Voltage and Operating Frequency Ranges Condition A: All H8S/2245 Group products VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B: HD6432246, HD6432245, HD6432244, HD6432243, HD6432242, HD6432241R, HD6412240 VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 13 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C: All H8S/2245 Group products VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to 20 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Rev.3.00 Mar. 26, 2007 Page 570 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Clock Supply Crystal Resonator Method Connection Operating Modules Condition A All Modules f (Hz) External Clock Input DTC, TPU, SCI, A/D Converter f (Hz) CPU, I/O Ports, Bus Controller, 8-Bit Timers, Interrupt Controller, WDT 20 M 10 M 20 M 10 M 2M 32 k 0 2.7 4.5 5.5 VCC (V) 2M 32 k 0 2.7 4.5 5.5 VCC (V) f (Hz) f (Hz) Condition B 20 M 13 M 10 M 20 M 13 M 10 M 2M 32 k 0 2.7 4.5 5.5 VCC (V) 2M 32 k 0 2.7 4.5 5.5 VCC (V) f (Hz) Condition C 20 M 13 M 10 M 2M 32 k 0 2.7 4.5 5.5 VCC (V) Rev.3.00 Mar. 26, 2007 Page 571 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.3 DC Characteristics Table 19.3 lists the DC characteristics. Table 19.4 lists the permissible output currents. Table 19.3 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V* , Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Symbol - 1 Min 1.0 -- Typ -- -- -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit V V V V Test Conditions VT Schmitt trigger Port 2, input voltage IRQ0 to IRQ7 V + T VT -VT Input high voltage RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, A to G Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, A to G Output high voltage Output low voltage Input leakage current All output pins VOH All output pins VOL Ports 1, A to C RES STBY, NMI, MD2 to MD0 Port 4 | Iin | VIL VIH + - 0.4 VCC -0.7 VCC x 0.7 -- 2.0 2.0 -0.3 -0.3 -- -- -- -- VCC +0.3 VCC +0.3 V V AVCC +0.3 V 0.5 0.8 V V VCC -0.5 3.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 1.0 10.0 1.0 1.0 V V V V A IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 10 mA Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V A Rev.3.00 Mar. 26, 2007 Page 572 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Item Three-state leakage current (off state) Input pull-up MOS current Input capacitance Ports 1 to 3, 5, A to G Symbol ITSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC -0.5 V Ports A to E RES NMI All input pins except RES and NMI -IP Cin 50 -- -- -- -- -- -- -- 300 80 50 15 A pF pF pF Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25C Current 2 dissipation* Normal operation Sleep mode All module stop mode Medium speed (/32) mode Sleep, all module stop and medium speed (/32) mode Standby 3 mode* ICC* 4 -- -- -- -- 50 75 (5.0 V) (5.5 V) 35 55 (5.0 V) (5.5 V) 35 -- (5.0 V) 25 -- (5.0 V) 5.0 10 (5.0 V) (5.5 V) mA mA mA mA f = 20 MHz f = 20 MHz Reference value f = 20 MHz Reference value f = 20 MHz f = 20 MHz -- mA -- -- AlCC -- -- AlCC -- -- VRAM 2.0 0.01 -- 1.2 0.01 0.5 0.01 -- 5.0 20.0 2.0 5.0 0.8 5.0 -- A mA A mA A V Ta 50C 50C < Ta Analog power During A/D supply current conversion Idle Reference current During A/D conversion Idle RAM standby voltage Vref = 5.0 V Rev.3.00 Mar. 26, 2007 Page 573 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 2.0 (mA) + 0.67 (mA/(MHz x V)) x VCC x f [normal mode] ICC max = 2.0 (mA) + 0.48 (mA/(MHz x V)) x VCC x f [sleep mode] ICC max = 2.0 (mA) + 0.07 (mA/(MHz x V)) x VCC x f [sleep, all module stop and medium speed (/32) mode] Rev.3.00 Mar. 26, 2007 Page 574 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Table 19.3 DC Characteristics (2) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, 1 VSS = AVSS = 0 V* , Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Symbol - Min VCC x 0.2 -- Typ -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit V V V V Test Conditions VT Schmitt trigger Port 2, input voltage IRQ0 to IRQ7 V + T VT - VT Input high voltage RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, A to G Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, A to G Output high voltage Output low voltage All output pins VOH All output pins VOL Ports 1, A to C VIL VIH + - VCC x 0.07 -- VCC x 0.9 -- VCC x 0.7 VCC x 0.7 VCC x 0.7 -0.3 -0.3 -- -- -- -- -- VCC +0.3 VCC +0.3 V V AVCC +0.3 V VCC x 0.1 VCC x 0.2 0.8 V V VCC < 4.0 V VCC = 4.0 to 5.5 V V V V V IOH = -200 A IOH = -1 mA IOL = 1.6 mA VCC 4 V, IOL = 5 mA, 4 V < VCC 5 V, IOL = 10 mA Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V VCC -0.5 VCC -1.0 -- -- -- -- -- -- -- -- 0.4 1.0 Input leakage current RES STBY, NMI, MD2 to MD0 Port 4 Iin -- -- -- -- -- -- 10.0 1.0 1.0 A A Rev.3.00 Mar. 26, 2007 Page 575 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Item Three-state leakage current (off state) Input pullup current Input capacitance Ports 1 to 3, 5, A to G Symbol ITSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC -0.5 V Port A to E RES NMI All input pins except RES and NMI -IP Cin 10 -- -- -- -- -- -- -- 300 80 50 15 A pF pF pF VCC = 2.7 V to 5.5 V, Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25C Current 2 dissipation* Normal operation ICC* 4 -- -- -- 13 40 (3.0 V) (5.5 V) 18 52 (3.0 V) (5.5 V) 60 120 mA f = 10 MHz f = 13 MHz A mA f = 32 kHz, 5 VCC = 3.0 V* f = 10 MHz f = 13 MHz Sleep mode -- -- 9 28 (3.0 V) (5.5 V) 12 37 (3.0 V) (5.5 V) 9 -- (3.0 V) 12 -- (3.0 V) 6 -- (3.0 V) 8 -- (3.0 V) 1.5 6.0 (3.0 V) (5.5 V) 2.5 7.5 (3.0 V) (5.5 V) 30 60 All module stop mode -- -- mA Reference value f = 10 MHz Reference value f = 13 MHz Medium speed (/32) mode -- -- -- -- -- mA Reference value f = 10 MHz Reference value f = 13 MHz Sleep, all module stop and medium speed (/32) mode mA f = 10 MHz f = 13 MHz A f = 32 kHz, 5 VCC = 3.0 V* Rev.3.00 Mar. 26, 2007 Page 576 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Item Current 2 dissipation* Standby 3 mode* Symbol ICC* 4 Min -- -- Typ 0.01 -- 0.4 1.2 0.01 0.3 0.5 0.01 -- Max 5.0 20.0 1.0 -- 5.0 0.6 -- 5.0 -- Unit A mA mA A mA mA A V Test Conditions Ta 50C 50C < Ta AVCC = 3.0 V AVCC = 5.0 V Vref = 3.0 V Vref = 5.0 V Analog power During A/D supply current conversion Idle Reference power supply current During A/D conversion Idle RAM standby voltage AlCC -- -- -- AlCC -- -- -- VRAM 2.0 Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 2.0 (mA) + 0.67 (mA/(MHz x V)) x VCC x f [normal mode] ICC max = 2.0 (mA) + 0.48 (mA/(MHz x V)) x VCC x f [sleep mode] ICC max = 2.0 (mA) + 0.07 (mA/(MHz x V)) x VCC x f [sleep, all module stop and medium speed (/32) mode] 5. The current dissipation for 32-kHz operation is the value when the duty adjustment circuit is stopped. Rev.3.00 Mar. 26, 2007 Page 577 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Table 19.4 Permissible Output Currents Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, A to C Other output pins Total of 28 pins including ports 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min -- -- -- Typ -- -- -- Max 10 2.0 80 Unit mA mA mA -- -- 120 mA -- -- -- -- 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 19.4. 2. When driving a darlington pair or LED, always insert a current-limiting resister in the output line, as show in figures 19.1 and 19.2. H8S/2245 Group 2 k Port Darlington Pair Figure 19.1 Darlington Pair Drive Circuit (Example) Rev.3.00 Mar. 26, 2007 Page 578 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics H8S/2245 Group 600 Ports 1, A to C LED Figure 19.2 LED Drive Circuit (Example) 19.4 AC Characteristics Figure 19.3 show, the test conditions for the AC characteristics. 5V RL LSI output pin C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, G RL = 2.4 k RH = 12 k I/O timing test levels * Low level: 0.8 V * High level: 2.0 V C RH Figure 19.3 Output Load Circuit Rev.3.00 Mar. 26, 2007 Page 579 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.4.1 Clock Timing Table 19.5 lists the clock timing Table 19.5 Clock Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 13 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 Min 100 35 35 -- -- 20 Max 31250 -- -- 15 15 -- Condition B Min 75 25 25 -- -- 20 Max 31250 -- -- 10 10 -- Condition C Min 50 20 20 -- -- 10 Max 500 -- -- 5 5 -- Unit ns ns ns ns ns ms Figure 19.5 Test Conditions Figure 19.4 tOSC2 8 -- 8 -- 8 -- ms Figure 18.2 tDEXT 500 -- 500 -- 500 -- s Figure 19.5 Rev.3.00 Mar. 26, 2007 Page 580 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics tcyc tCH tCL tCr tCf Figure 19.4 System Clock Timing EXTAL tDEXT VCC tDEXT STBY NMI tOSC1 RES tOSC1 Figure 19.5 Oscillator Settling Timing Rev.3.00 Mar. 26, 2007 Page 581 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.4.2 Control Signal Timing Table 19.6 lists the control signal timing. Table 19.6 Control Signal Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 13 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85c (wide-range specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item RES setup time RES pulse width NMI reset setup time NMI reset hold time NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol tRESS tRESW tNMIRS tNMIRH tNMIS tNMIH tNMIW Min 200 20 200 200 200 10 200 Max -- -- -- -- -- -- -- Condition B Min 200 20 200 200 200 10 200 Max -- -- -- -- -- -- -- Condition C Min 200 20 200 200 150 10 200 Max -- -- -- -- -- -- -- ns ns Figure 19.7 Unit ns tcyc ns Test Conditions Figure 19.6 tIRQS tIRQH tIRQW 200 10 200 -- -- -- 200 10 200 -- -- -- 150 10 200 -- -- -- ns ns ns Rev.3.00 Mar. 26, 2007 Page 582 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics tRESS RES tRESW tNMIRS NMI tRESS tNMIRH Figure 19.6 Reset Input Timing tNMIS NMI tNMIW tNMIH IRQi (i = 0 to 2) tIRQS IRQ Edge input tIRQS IRQ Level input tIRQW tIRQH Figure 19.7 Interrupt Input Timing Rev.3.00 Mar. 26, 2007 Page 583 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.4.3 Bus Timing Table 19.7 lists the bus timing. Table 19.7 Bus Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 13 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Address delay time Address setup time Address hold time CS delay time AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Symbol tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 Min -- 0.5 x tcyc -30 0.5 x tcyc -20 -- -- -- -- 30 0 -- -- -- -- Max 40 -- -- 40 60 60 60 -- -- 1.0 x tcyc -50 1.5 x tcyc -50 2.0 x tcyc -50 2.5 x tcyc -50 Condition B Min -- 0.5 x tcyc -20 0.5 x tcyc -15 -- -- -- -- 30 0 -- -- -- -- Max 35 -- -- 35 50 45 45 -- -- 1.0 x tcyc -55 1.5 x tcyc -55 2.0 x tcyc -55 2.5 x tcyc -55 Condition C Min -- 0.5 x tcyc -15 0.5 x tcyc -10 -- -- -- -- 15 0 -- -- -- -- Max 20 -- -- 20 30 30 30 -- -- 1.0 x tcyc -25 1.5 x tcyc -25 2.0 x tcyc -25 2.5 x tcyc -25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 19.8 to Figure 19.12 Rev.3.00 Mar. 26, 2007 Page 584 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Condition A Item Read data access time 5 WR delay time 1 WR delay time 2 Symbol tACC5 tWRD1 tWRD2 Min -- -- -- 1.0 x tcyc -40 1.5 x tcyc -40 -- 0 20 60 10 60 -- -- -- Max 3.0 x tcyc -50 60 60 -- -- 60 -- -- -- -- -- 60 100 60 Condition B Min -- -- -- 1.0 x tcyc -30 1.5 x tcyc -30 -- 0 20 50 10 50 -- -- -- Max 3.0 x tcyc -55 45 50 -- -- 60 -- -- -- -- -- 50 80 50 Condition C Min -- -- -- 1.0 x tcyc -20 1.5 x tcyc -20 -- 0 10 30 5 30 -- -- -- Max 3.0 x tcyc -25 30 30 -- -- 30 -- -- -- -- -- 30 50 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 19.14 Figure 19.13 Figure 19.10 Test Conditions Figure 19.8 to Figure 19.12 WR pulse width 1 tWSW1 WR pulse width 2 tWSW2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BACK delay time Bus-floating time BREQO delay time tWDD tWDS tWDH tWTS tWTH tBACD tBZD tBRQOD BREQ setup time tBRQS Rev.3.00 Mar. 26, 2007 Page 585 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics T1 tAD A23 to A0 tCSD CS3 to CS0 tASD AS tAS T2 tAH tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tRDS tRDH tWRD2 HWR, LWR (write) tAS tWDD D15 to D0 (write) tWSW1 tWRD2 tAH tWDH Figure 19.8 Basic Bus Timing (Two-State Access) Rev.3.00 Mar. 26, 2007 Page 586 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics T1 T2 T3 tAD A23 to A0 tCSD CS3 to CS0 tASD AS tASD tAS tAH tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 19.9 Basic Bus Timing (Three-State Access) Rev.3.00 Mar. 26, 2007 Page 587 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics T1 T2 TW T3 A23 to A0 CS3 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 19.10 Basic Bus Timing (Three-State Access with One Wait State) Rev.3.00 Mar. 26, 2007 Page 588 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics T1 T2 or T3 T1 T2 tAD A23 to A0 tAS CS3 to CS0 tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH tASD tAH Figure 19.11 Burst ROM Access Timing (Two-State Access) Rev.3.00 Mar. 26, 2007 Page 589 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics T1 T2 or T3 T1 tAD A23 to A0 CS3 to CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 19.12 Burst ROM Access Timing (One-State Access) Rev.3.00 Mar. 26, 2007 Page 590 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS3 to CS0, AS, RD, HWR, LWR tBACD tBZD Figure 19.13 External Bus Release Timing tBRQOD tBRQOD BREQO Figure 19.14 External Bus Request Output Timing Rev.3.00 Mar. 26, 2007 Page 591 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.4.4 Timing of On-Chip Supporting Modules Table 19.8 lists the timing of on-chip supporting modules. Table 19.8 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 10 MHz (I/O port, TMR, WDT), = 2 to 10 MHz (TPU, SCI, A/D converter), Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 32 kHz to 13 MHz (I/O port, TMR, WDT), = 2 to 13 MHz (TPU, SCI, A/D converter), Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Condition B Condition C Item I/O port Symbol Min Output data delay tPWD time Input data setup time Input data hold time TPU Timer output delay time tPRS tPRH tTOCD -- 50 50 -- 50 50 1.5 2.5 Max 100 -- -- 100 -- -- -- -- Min -- 50 50 -- 40 40 1.5 2.5 Max 75 -- -- 75 -- -- -- -- Min -- 30 30 -- 30 30 1.5 2.5 Max 50 -- -- 50 -- -- -- -- ns tcyc Figure 19.17 ns Figure 19.16 Test Unit Conditions ns Figure 19.15 Timer input setup tTICS time Timer clock input setup time Timer clock pulse width Single edge Both edges tTCKS tTCKWH tTCKWL Rev.3.00 Mar. 26, 2007 Page 592 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics Condition A Condition B Condition C Item 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width WDT SCI Single edge Both edges Symbol Min tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD -- 50 50 1.5 2.5 -- 4 6 tSCKW tSCKr tSCKf tTXD tRXS 0.4 -- -- -- 100 Max 100 -- -- -- -- 100 -- -- 0.6 1.5 1.5 100 -- Min -- 50 50 1.5 2.5 -- 4 6 0.4 -- -- -- 75 Max 75 -- -- -- -- 75 -- -- 0.6 1.5 1.5 75 -- Min -- 30 30 1.5 2.5 -- 4 6 0.4 -- -- -- 50 Max 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- ns ns Figure 19.23 tScyc tcyc ns tcyc Figure 19.21 Figure 19.22 Test Unit Conditions ns ns ns tcyc Figure 19.18 Figure 19.20 Figure 19.19 Overflow output delay time Input clock cycle Asynchro- tScyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time tRXH 100 -- 75 -- 50 -- ns tTRGS 50 -- 40 -- 30 -- ns Figure 19.24 Rev.3.00 Mar. 26, 2007 Page 593 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics T1 T2 tPRS Ports 1 to 5, A to G (read) tPRH tPWD Ports 1 to 3, 5, A to G (write) Figure 19.15 I/O Port Input/Output Timing tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 19.16 TPU Input/Output Timing tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 19.17 TPU Clock Input Timing Rev.3.00 Mar. 26, 2007 Page 594 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics tTMOD TMO0, TMO1 Figure 19.18 8-Bit Timer Output Timing tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 19.19 8-Bit Timer Clock Input Timing tTMRS TMRI0, TMRI1 Figure 19.20 8-Bit Timer Reset Input Timing tWOVD WDTOVF tWOVD Figure 19.21 WDT Output Timing Rev.3.00 Mar. 26, 2007 Page 595 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics tSCKW SCK0 to SCK2 tSCKr tSCKf tScyc Figure 19.22 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 Transmit data tRXS RxD0 to RxD2 Receive data tRXH Figure 19.23 SCI Input/Output Timing Synchronous Mode tTRGS ADTRG Figure 19.24 A/D Converter External Trigger Input Timing Rev.3.00 Mar. 26, 2007 Page 596 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.5 A/D Conversion Characteristics Table 19.9 lists the A/D conversion characteristics. Table 19.9 A/D Conversion Characteristics Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Resolution Conversion time Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 13.1 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 -- 20 10*1 5* 2 Condition B Min 10 9.8 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 -- 20 10*1 5* 2 Condition C Min 10 6.5 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 -- 20 10*3 5* 4 Unit bits s pF k 6.0 4.0 4.0 0.5 8.0 6.0 4.0 4.0 0.5 8.0 3.0 2.0 2.0 0.5 4.0 LSB LSB LSB LSB LSB Notes: 1. 2. 3. 4. 4.0 AVCC 5.5 V 2.7 V AVCC < 4.0 V 12 MHz > 12 MHz Rev.3.00 Mar. 26, 2007 Page 597 of 772 REJ09B0355-0300 Section 19 Electrical Characteristics 19.6 Usage Notes Although both the ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT version, a similar evaluation should also be performed using the mask ROM version. Rev.3.00 Mar. 26, 2007 Page 598 of 772 REJ09B0355-0300 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Move Logical NOT (logical complement) Contents of effective address of the operand 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.3.00 Mar. 26, 2007 Page 599 of 772 REJ09B0355-0300 Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of instruction Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction * 0 1 -- Rev.3.00 Mar. 26, 2007 Page 600 of 772 REJ09B0355-0300 Table A.1 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B2 B B B B B B B B B B B B B B B W4 W W 2 2 6 4 2 Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 Rs16Rd16 @ERsRd16 2 8 Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd 4 Rs8@(d:16,ERd) 2 Rs8@ERd 6 @aa:32Rd8 4 @aa:16Rd8 2 @aa:8Rd8 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 @ERsRd8,ERs32+1ERs32 ---- 8 @(d:32,ERs)Rd8 ---- 4 @(d:16,ERs)Rd8 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 @ERsRd8 ---- 0-- 2 Rs8Rd8 ---- 0-- #xx:8Rd8 ---- 0-- 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 Operation I H N Z V C Normal Advanced MOV MOV.B #xx:8,Rd Instruction Set MOV.B Rs,Rd (1) Data Transfer Instructions MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 601 of 772 REJ09B0355-0300 MOV.W @ERs,Rd MOV.W Rs,Rd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic W W W W W W W W W W W L6 L L L L L L L 4 6 8 10 6 4 2 6 4 Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 @aa:32ERd32 2 8 Rs16@(d:32,ERd) 4 Rs16@(d:16,ERd) 2 Rs16@ERd 6 @aa:32Rd16 4 @aa:16Rd16 ---- ---- ---- ---- ---- 2 @ERsRd16,ERs32+2ERs32 -- -- 8 @(d:32,ERs)Rd16 ---- 4 @(d:16,ERs)Rd16 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- Operation I H N Z V C Normal Advanced 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 MOV MOV.W @(d:16,ERs),Rd Appendix A Instruction Set MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd ERd32-2ERd32,Rs16@ERd -- -- MOV.L @aa:32,ERd Rev.3.00 Mar. 26, 2007 Page 602 of 772 REJ09B0355-0300 MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic L 6 10 4 6 8 2 4 2 4 4 SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeated for each register restored L 4 (SP-4SP,ERn32@SP) Repeated for each register saved Cannot be used in the H8S/2245 Group Cannot be used in the H8S/2245 Group @SPRn16,SP+2SP @SPERn32,SP+4SP ERs32@aa:32 ERs32@aa:16 ERd32-4ERd32,ERs32@ERd -- -- ---- ---- ---- ---- ---- ---- ERs32@(d:32,ERd) ---- ERs32@(d:16,ERd) ---- 4 ERs32@ERd ---- 0 0 0 0 0 0 0 0 0 0 Operation I H N Z V C Normal Advanced -- -- -- -- -- -- -- -- -- -- ------------ 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L L L L W L W L L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.W Rn POP.L ERn PUSH.L ERn LDM* LDM @SP+,(ERm-ERn) STM* STM (ERm-ERn),@-SP ------------ PUSH PUSH.W Rn 7/9/11 [1] MOVFPE MOVFPE @aa:16,Rd [2] [2] MOVTPE MOVTPE Rs,@aa:16 Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 603 of 772 REJ09B0355-0300 Note: * Only register ER0 to ER6 should be used when using the STM/LDM instruction. Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B2 B W4 W L6 L B2 B L L L B W W L L B 2 2 2 2 2 2 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjustRd8 2 ERd32+4ERd32 2 ERd32+2ERd32 2 ERd32+1ERd32 2 Rd8+Rs8+CRd8 Rd8+#xx:8+CRd8 -- -- 2 ERd32+ERs32ERd32 -- [4] ERd32+#xx:32ERd32 -- [4] 2 Rd16+Rs16Rd16 -- [3] Rd16+#xx:16Rd16 -- [3] 2 Rd8+Rs8Rd8 -- Rd8+#xx:8Rd8 -- Operation I H N Z V C Normal Advanced 1 1 2 1 3 1 [5] [5] 1 1 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- 1 1 1 1 1 1 1 1 ADD ADD.B #xx:8,Rd (2) Arithmetic Instructions Appendix A Instruction Set ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd Rev.3.00 Mar. 26, 2007 Page 604 of 772 REJ09B0355-0300 * 1 ADD.L ERs,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA DAA Rd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B W4 Rd16-#xx:16Rd16 2 ERd32-#xx:32ERd32 2 Rd8-#xx:8-CRd8 2 2 2 2 2 2 2 2 2 2 2 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjustRd8 Rd8xRs8Rd16 (unsigned multiplication) W 2 Rd16xRs16ERd32 (unsigned multiplication) ERd32-2ERd32 ERd32-4ERd32 ERd32-1ERd32 Rd8-Rs8-CRd8 ERd32-ERs32ERd32 -- [4] -- [4] -- -- Rd16-Rs16Rd16 -- [3] -- [3] W L6 L B2 B L L L B W W L L B B 2 Rd8-Rs8Rd8 -- Operation I H N Z V C Normal Advanced 1 2 1 3 1 [5] [5] 1 1 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- ------------ 1 1 1 1 1 1 1 1 1 12 SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX Rs,Rd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS DAS Rd MULXU MULXU.B Rs,Rd Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 605 of 772 REJ09B0355-0300 MULXU.W Rs,ERd ------------ SUBX SUBX #xx:8,Rd 20 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation I H N Z V C Normal Advanced MULXS B (signed multiplication) 4 Appendix A Instruction Set MULXS.B Rs,Rd MULXS.W Rs,ERd (signed multiplication) B RdL: quotient) (unsigned division) W 2 2 W 4 Rd16xRs16ERd32 ---- Rd8xRs8Rd16 ---- ---- 13 ---- 21 DIVXU DIVXU.B Rs,Rd Rd16/Rs8Rd16 (RdH: remainder, -- -- [6] [7] -- -- 12 CMP.B Rs,Rd W4 W L6 L B W L 2 2 2 2 2 B 2 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 0-ERd32ERd32 -- NEG.L ERd -- Rev.3.00 Mar. 26, 2007 Page 606 of 772 REJ09B0355-0300 ERd32/Rs16ERd32 (Ed: remainder, -- -- [6] [7] -- -- Rd: quotient) (unsigned division) B 4 Rd16/Rs8Rd16 (RdH: remainder, -- -- [8] [7] -- -- RdL: quotient) (signed division) W 4 ERd32/Rs16ERd32 (Ed: remainder, -- -- [8] [7] -- -- Rd: quotient) (signed division) B2 Rd8-#xx:8 -- 1 1 -- [3] -- [3] -- [4] -- [4] -- -- 2 1 3 1 1 1 1 21 13 20 DIVXU.W Rs,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd CMP CMP.B #xx:8,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.B Rd NEG.W Rd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation I H N Z V C Normal Advanced EXTU.L ERd L 2 0( ---- 0 EXTU W ( EXTU.W Rd 0( ---- 0 0-- 0-- 1 1 ( TAS* B ( TAS @ERd Note: * Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. @ERd-0CCR set, (1) ---- EXTS.L ERd L 2 ( ---- EXTS EXTS.W Rd W 2 0-- 1 0-- 1 0-- 4 Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 607 of 772 REJ09B0355-0300 Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Condition Code -- No. of States*1 Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 L B W L 2 2 2 4 2 2 4 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8Rd8 Rd16Rd16 ERd32ERd32 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd16#xx:16Rd16 2 Rd8Rs8Rd8 Rd8#xx:8Rd8 4 ERd32ERs32ERd32 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ERd32#xx:32ERd32 ---- 2 Rd16Rs16Rd16 ---- Rd16#xx:16Rd16 ---- 2 Rd8Rs8Rd8 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- ---- 0-- Rd8#xx:8Rd8 ---- 0-- Operation I H N Z V C Normal Advanced 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 (3) Logical Instructions AND AND.B #xx:8,Rd Appendix A Instruction Set AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd NOT.L ERd Rev.3.00 Mar. 26, 2007 Page 608 of 772 REJ09B0355-0300 AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- (4) Shift Instructions Mnemonic B B W W L L B B W W MSB L L B B W W L L 2 2 2 2 C MSB LSB 2 0 2 2 2 2 2 LSB C 2 2 2 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 C MSB ---- LSB 2 0 ---- 2 ---- 2 ---- Operation I H N Z V C Normal Advanced 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 609 of 772 REJ09B0355-0300 SHLL.L #2,ERd SHLL.L ERd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B W W L L B B W W C MSB L L B B W W L L 2 2 2 2 MSB LSB C 2 2 2 2 2 2 LSB 2 2 2 2 2 MSB LSB C 2 0 ---- 0 ---- 0 ---- 0 ---- 0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 ---- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ---- 0 0 Operation I H N Z V C Normal Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SHLR SHLR.B Rd Appendix A Instruction Set SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXR.L #2,ERd Rev.3.00 Mar. 26, 2007 Page 610 of 772 REJ09B0355-0300 ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B W W C MSB L L B B W W MSB L L 2 2 2 2 LSB C 2 2 2 2 2 LSB ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 ---- 2 ---- 2 ---- 0 0 0 0 0 0 0 0 0 0 0 0 Operation I H N Z V C Normal Advanced 1 1 1 1 1 1 1 1 1 1 1 1 ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L #2,ERd ROTR.L ERd Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 611 of 772 REJ09B0355-0300 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B B B B B B B B B B B B B B B B B B 6 4 4 2 8 6 4 4 2 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 8 (Rn8 of @aa:32)1 6 (Rn8 of @aa:16)1 4 (Rn8 of @aa:8)1 4 (Rn8 of @ERd)1 2 (Rn8 of Rd8)1 8 (#xx:3 of @aa:32)1 6 (#xx:3 of @aa:16)1 4 (#xx:3 of @aa:8)1 4 (#xx:3 of @ERd)1 -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- 2 (#xx:3 of Rd8)1 -- ---- -- -- -- Operation I H N Z V C Normal Advanced 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 BSET BSET #xx:3,Rd Appendix A Instruction Set BSET #xx:3,@ERd BSET #xx:3,@aa:8 (5) Bit-Manipulation Instructions BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 Rev.3.00 Mar. 26, 2007 Page 612 of 772 REJ09B0355-0300 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B B [ (#xx:3 of @ERd)] B [ (#xx:3 of @aa:8)] B [ (#xx:3 of @aa:16)] B 8 (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] B B B B 6 4 4 2 (Rn8 of Rd8)[ (Rn8 of Rd8)] 6 (#xx:3 of @aa:16) 4 (#xx:3 of @aa:8) 4 (#xx:3 of @ERd) 2 8 (Rn8 of @aa:32)0 Operation I H N Z V C Normal Advanced ------------ 6 1 4 BCLR BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd (#xx:3 of Rd8)[ (#xx:3 of Rd8)] -- -- -- -- -- -- ------------ BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 ------------ 4 BNOT #xx:3,@aa:16 ------------ 5 BNOT #xx:3,@aa:32 ------------ 6 BNOT Rn,Rd ------------ 1 4 4 BNOT Rn,@ERd (Rn8 of @ERd)[ (Rn8 of @ERd)] -- -- -- -- -- -- (Rn8 of @aa:8)[ (Rn8 of @aa:8)] -- -- -- -- -- -- (Rn8 of @aa:16) [ (Rn8 of @aa:16)] ------------ BNOT Rn,@aa:8 BNOT Rn,@aa:16 5 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32) [ (Rn8 of @aa:32)] ------------ 6 BTST B B B 4 BTST #xx:3,Rd B 2 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z 4 6 (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z ------ ------ ------ ------ ---- ---- ---- ---- 1 3 3 4 BTST #xx:3,@ERd Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 613 of 772 REJ09B0355-0300 BTST #xx:3,@aa:16 BTST #xx:3,@aa:8 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B B B B B B B B B B B B B B B B B B 4 4 2 8 6 4 4 2 8 6 4 (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) 4 (#xx:3 of @ERd)C 2 (#xx:3 of Rd8)C 8 (Rn8 of @aa:32)Z 6 (Rn8 of @aa:16)Z 4 (Rn8 of @aa:8)Z 4 (Rn8 of @ERd)Z ------ ------ ------ ------ 2 (Rn8 of Rd8)Z ------ 8 (#xx:3 of @aa:32)Z ------ ---- ---- ---- ---- ---- ---- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- Operation I H N Z V C Normal Advanced 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ------------ ------------ ------------ 1 4 4 BTST BTST #xx:3,@aa:32 Appendix A Instruction Set BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:32 BILD #xx:3,@aa:32 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 Rev.3.00 Mar. 26, 2007 Page 614 of 772 REJ09B0355-0300 BTST Rn,@aa:16 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B B B B B B B B B B B B B B B B B B 4 2 8 6 4 4 2 8 6 4 4 2 C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C 8 C(#xx:3 of @aa:32) 6 C(#xx:3 of @aa:16) 4 C(#xx:3 of @aa:8) 4 C(#xx:3 of @ERd) 2 C(#xx:3 of Rd8) 8 C(#xx:3 of @aa:32) 6 C(#xx:3 of @aa:16) Operation I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 615 of 772 REJ09B0355-0300 BOR #xx:3,@ERd BOR BOR #xx:3,Rd Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B B B B B B B B B B B B B B B B B 6 8 4 4 2 8 6 4 4 2 C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C 8 6 C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C 4 C[ (#xx:3 of @aa:8)]C 4 C[ (#xx:3 of @ERd)]C 2 C[ (#xx:3 of Rd8)]C 8 C(#xx:3 of @aa:32)C 6 C(#xx:3 of @aa:16)C 4 C(#xx:3 of @aa:8)C ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- Operation I H N Z V C Normal Advanced 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 BOR BOR #xx:3,@aa:8 Appendix A Instruction Set BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIXOR #xx:3,@aa:32 Rev.3.00 Mar. 26, 2007 Page 616 of 772 REJ09B0355-0300 BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition Operand Size No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 V=0 2 4 Z=1 2 4 Z=0 2 4 C=1 2 4 C=0 2 CZ=1 4 2 CZ=0 4 2 else next; Never 4 PCPC+d -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- 2 if condition is true then Always -- -- -- ---- -- I H N Z V C Normal Advanced 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 (6) Branch Instructions Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 617 of 772 REJ09B0355-0300 BVC d:16 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition Operand Size No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 2 4 2 4 NV=1 2 4 NV=0 2 N=1 4 2 N=0 4 2 V=1 -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- -- ---- Z(NV)=0 -- -- -- -- -- -- -- -- -- -- ---- Z(NV)=1 -- -- -- -- -- -- -- -- -- -- ---- I H N Z V C Normal Advanced 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Bcc BVS d:8 Appendix A Instruction Set BVS d:16 If condition is true then PC PC + d else next; BPL d:8 BPL d:16 BMI d:8 BMI d:16 Rev.3.00 Mar. 26, 2007 Page 618 of 772 REJ09B0355-0300 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic -- -- -- -- -- -- -- -- -- 2 PC@SP+ 2 PC@-SP,PC@aa:8 4 PC@-SP,PCaa:24 2 PC@-SP,PCERn 4 PC@-SP,PCPC+d:16 2 PC@-SP,PCPC+d:8 2 PC@aa:8 4 PCaa:24 2 PCERn Operation I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 4 3 4 3 4 4 4 2 3 5 4 5 4 5 6 5 JMP JMP @ERn JMP @aa:24 JMP @@aa:8 BSR BSR d:8 BSR d:16 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 619 of 772 REJ09B0355-0300 Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic -- EXR@-SP, Operation PC@-SP,CCR@-SP, 1 -- -- -- ---- 7 [9] I H N Z V C Normal Advanced 8 [9] Appendix A Instruction Set TRAPA EXR@SP+,CCR@SP+, PC@SP+ -- TRAPA #xx:2 (7) System Control Instructions RTE Transition to power-down state #xx:8CCR #xx:8EXR 2 2 4 4 6 6 10 10 4 4 6 6 8 8 @ERsEXR @(d:16,ERs)CCR @(d:16,ERs)EXR @(d:32,ERs)CCR @(d:32,ERs)EXR @ERsCCR,ERs32+2ERs32 @ERsEXR,ERs32+2ERs32 @aa:16CCR @aa:16EXR @aa:32CCR @aa:32EXR @ERsCCR Rs8EXR Rs8CCR RTE -- 5 [9] SLEEP B2 B4 B B W W W W W W W W W W W W SLEEP -- -- -- -- ---- 2 1 2 LDC LDC #xx:8,CCR LDC Rs,CCR LDC Rs,EXR -- -- -- -- ---- LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR -- -- -- -- ---- Rev.3.00 Mar. 26, 2007 Page 620 of 772 REJ09B0355-0300 -- -- -- -- ---- 1 1 3 -- -- -- -- ---- 3 4 4 6 -- -- -- -- ---- 6 4 -- -- -- -- ---- 4 4 -- -- -- -- ---- 4 5 -- -- -- -- ---- 5 LDC #xx:8,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic B B W W W W W W W W W W W W B2 B4 B2 B4 B2 B4 -- 2 8 8 6 6 4 CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR PCPC+2 4 10 EXR@(d:32,ERd) 10 CCR@(d:32,ERd) 6 EXR@(d:16,ERd) 6 CCR@(d:16,ERd) 4 EXR@ERd 4 CCR@ERd 2 EXRRd8 2 CCRRd8 Operation I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 1 3 3 4 4 6 6 4 ------------ ------------ ------------ ------------ ------------ 4 4 4 5 5 STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd ERd32-2ERd32,CCR@ERd -- -- -- -- -- -- ERd32-2ERd32,EXR@ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR 1 ------------ 2 ANDC #xx:8,EXR ORC ORC #xx:8,CCR 1 ------------ 2 ORC #xx:8,EXR XORC XORC #xx:8,CCR 1 ------------ ------------ 2 1 XORC #xx:8,EXR Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 621 of 772 REJ09B0355-0300 NOP NOP Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; ------------ -- 4 Appendix A Instruction Set (8) Program Transfer Instructions EEPMOV EEPMOV.B I H N Z V C Normal Advanced ------------ 4+2n*2 Rev.3.00 Mar. 26, 2007 Page 622 of 772 REJ09B0355-0300 -- 4 4+2n*2 EEPMOV.W Notes: 1. 2. [1] [2] [3] [4] [5] [6] [7] [8] [9] The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial value of R4L or R4. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. Cannot be used in the H8S/2245 Group. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. One additional state is required for execution when EXR is valid. A.2 Table A.2 Instruction when most significant bit of BH is 0. 2nd byte BH BL Instruction when most significant bit of BH is 1. Instruction code 1st byte AH AL AL 3 4 ORC OR MOV.B XOR AND Table A.2(2) SUB CMP XORC ANDC LDC ADD MOV 5 6 7 8 9 C D A B LDC Table A.2(2) AH 0 1 2 E ADDX SUBX F 0 NOP STC Operation Code Map 1 Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2(2) Table A.2 shows the operation code map. Operation Code Map (1) 2 3 BLS BCC RTS MOV MOV Table A.2(2) BSR RTE TRAPA JMP Table A.2(2) BNE BEQ BVC BVS BPL BMI DIVXU BTST BCS BGE BSR MOV Table A.2(3) BLT BGT JSR BLE 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 ADD ADDX CMP SUBX OR XOR AND MOV BST XOR AND OR BIST BLD BOR BXOR BAND BILD BIOR BIXOR BIAND Table A.2(2) Table A.2(2) EEPMOV 8 9 A B C D E Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 623 of 772 REJ09B0355-0300 F Table A.2 Instruction code BH BL 1st byte 2nd byte AH AL BH 2 7 SLEEP ADD INC INC ADDS MOV SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU NEG ROTR NEG SUB DEC DEC SUBS CMP BHI MOV CMP CMP SUB OR XOR SUB OR XOR Table A.2(4) MOVFPE AND AND BLS BCC BCS BNE BEQ BVC MOV BVS BPL MOV BMI BGE MOVTPE ROTL SHAR SHAL SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR Table A.2(3) 8 9 C A B STM STC LDC 3 4 5 6 D AH AL 0 1 E TAS F Table A.2(3) Appendix A Instruction Set 01 MOV LDM Table A.2(3) 0A INC 0B ADDS INC INC Operation Code Map (2) Rev.3.00 Mar. 26, 2007 Page 624 of 772 REJ09B0355-0300 SHAL SHAR ROTL ROTR EXTS EXTS DEC DEC BLT BGT BLE 0F DAA 10 SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS 1F DAS 58 BRA BRN 6A MOV Table A.2(4) 79 MOV ADD 7A MOV ADD Table A.2 Instruction code BH BL CH CL DH DL 1st byte 2nd byte 3rd byte 4th byte AH AL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL 2 MULXS DIVXS OR BTST BTST BCLR BCLR BTST BTST BCLR BCLR XOR AND 3 4 5 6 7 8 9 A B AH AL BH BL CH 0 1 C D E F Operation Code Map (3) 01C05 MULXS 01D05 DIVXS 01F06 7Cr06*1 7Cr07*1 7Dr06*1 BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 7Dr07*1 BSET BNOT 7Eaa6*2 7Eaa7*2 7Faa6*2 BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 7Faa7*2 BSET BNOT Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 625 of 772 REJ09B0355-0300 Notes: 1. r is the register specification field. 2. aa is the absolute address specification. Table A.2 Instruction code BH BL CH CL DH DL EH EL FH FL 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte AH AL Appendix A Instruction Set Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 2 4 5 6 7 8 9 A B C BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 3 D E F EL AHALBHBLCHCLDHDLEH 0 1 6A10aaaa6* Operation Code Map (4) 6A10aaaa7* 6A18aaaa6* BCLR Rev.3.00 Mar. 26, 2007 Page 626 of 772 REJ09B0355-0300 2nd byte BH BL CH CL DH DL EH EL FH 3rd byte 4th byte 5th byte 6th byte FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. 2 4 5 6 BTST 3 7 8 9 A B C D E F BCLR BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BSET BNOT 6A18aaaa7* Instruction code 1st byte AH AL GL AHALBHBL ... FHFLGH 0 1 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET BNOT 6A38aaaaaaaa7* Note: * aa is the absolute address specification Appendix A Instruction Set A.3 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8S/2000 CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required for each cycle, depending on its size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.4: I = L = 2, From table A.3: SI = 4, SL = 2 J=K=M=N=0 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table A.4: I = J = K = 2, From table A.3: SI = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 L=M=N=0 Rev.3.00 Mar. 26, 2007 Page 627 of 772 REJ09B0355-0300 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions On-Chip Supporting Module On-Chip Memory 8-Bit Bus 4 16-Bit Bus 2 External Device 8-Bit Bus 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus 2-State Access 2 3-State Access 3+m Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN 1 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Rev.3.00 Mar. 26, 2007 Page 628 of 772 REJ09B0355-0300 Appendix A Instruction Set Table A.4 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read J Stack Byte Data Operation Access K L Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ADDS ADDX AND ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC BAND AND.B #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 1 1 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) 1 1 Rev.3.00 Mar. 26, 2007 Page 629 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction Bcc Mnemonic BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Stack Byte Data Operation Access K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 Rev.3.00 Mar. 26, 2007 Page 630 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction BIST Mnemonic BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Stack Byte Data Operation Access K L 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 Word Data Access M Internal Operation N Rev.3.00 Mar. 26, 2007 Page 631 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction BSR Mnemonic BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXU DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd Normal Advanced Normal Advanced I 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 Stack Byte Data Operation Access K 1 2 1 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 L Word Data Access M Internal Operation N 1 1 11 19 11 19 Rev.3.00 Mar. 26, 2007 Page 632 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction EEPMOV EXTS EXTU INC Mnemonic EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM*3 LDM.L @SP+,(ERn-ERn+1) LDM.L @SP+,(ERn-ERn+2) LDM.L @SP+,(ERn-ERn+3) Normal Advanced Normal Advanced Normal Advanced Normal Advanced I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 Stack Byte Data Operation Access K L 2n + 2*2 2n + 2* 2 Word Data Access M Internal Operation N 1 1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 Rev.3.00 Mar. 26, 2007 Page 633 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction MOV Mnemonic MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) I 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 Stack Byte Data Operation Access K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 1 Rev.3.00 Mar. 26, 2007 Page 634 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction MOV Mnemonic MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MULXU NEG MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC POP PUSH ROTL ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd I 2 3 4 Stack Byte Data Operation Access K L Word Data Access M 2 2 2 Internal Operation N 1 Cannot be used in the H8S/2245 Group Cannot be used in the H8S/2245 Group 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 11 19 11 19 Rev.3.00 Mar. 26, 2007 Page 635 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction ROTXL Mnemonic ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP Normal Advanced I 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Stack Byte Data Operation Access K L Word Data Access M Internal Operation N 2/3* 1 2 1 1 1 1 1 Rev.3.00 Mar. 26, 2007 Page 636 of 772 REJ09B0355-0300 Appendix A Instruction Set Branch Address Read J Instruction Fetch Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM*3 STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX TAS*4 TRAPA XOR SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #xx:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Normal Advanced I 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 1 2 1 3 1 1 1 1 2 2 2 1 1 2 1 3 2 1 2 Stack Byte Data Operation Access K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 2 1 2 2/3*1 2/3*1 2 2 Notes: 1. 2. 3. 4. 2 when EXR is invalid, 3 when EXR is valid. When n bytes of data are transferred. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Mar. 26, 2007 Page 637 of 772 REJ09B0355-0300 Appendix B Register Field Appendix B Register Field B.1 Register Addresses Module Name DTC Bus Width (Bit) 16/32* Address Register (Low) Name H'F800 to H'FBFF MRA MRB SAR DAR CRA CRB H'FEB0 H'FEB1 H'FEB2 H'FEB4 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF H'FEC0 H'FEC1 H'FEC2 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FF2C H'FF2D H'FF2E H'FF2F P1DDR P2DDR P3DDR P5DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR ICRA ICRB ICRC ABWCR ASTCR WCRH WCRL BCRH BCRL ISCRH ISCRL IER ISR Bit 7 SM1 CHNE Bit 6 SM0 DISEL Bit 5 DM1 -- Bit 4 DM0 -- Bit 3 MD1 -- Bit 2 MD0 -- Bit 1 DTS -- Bit 0 Sz -- P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 -- -- -- -- -- -- P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 -- -- -- -- P53DDR P52DDR P51DDR P50DDR Port 5 PA3DDR PA2DDR PA1DDR PA0DDR Port A 8 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Port C PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Port D PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Port E PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Port F -- ICRA7 -- ICRC7 ABW7 AST7 W71 W31 ICIS1 BRLE -- ICRA6 ICRB6 ICRC6 ABW6 AST6 W70 W30 ICIS0 -- ICRA5 ICRB5 -- ABW5 AST5 W61 W21 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Port G ICRA4 ICRB4 ICRC4 ABW4 AST4 W60 W20 ICRA3 ICRB 3 ICRC3 ABW3 AST3 W51 W11 ICRA2 -- ICRC2 ABW2 AST2 W50 W10 ICRA1 -- ICRC1 ABW1 AST1 W41 W01 -- -- -- -- ICRC0 ABW0 AST0 W40 W00 -- WAITE 8 Bus controller 8 Interrupt controller 8 BRSTRM BRSTS1 BRSTS0 -- -- -- ASS BREQOE EAE IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt controller IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IRQ7E IRQ7F IRQ6E IRQ6F IRQ5E IRQ5F IRQ4E IRQ4F IRQ3E IRQ3F IRQ2E IRQ2F IRQ1E IRQ1F IRQ0E IRQ0F Rev.3.00 Mar. 26, 2007 Page 638 of 772 REJ09B0355-0300 Appendix B Register Field Bus Width (Bit) 8 Address Register (Low) Name H'FF30 H'FF31 H'FF32 H'FF33 H'FF34 H'FF35 H'FF37 H'FF38 H'FF39 H'FF3A DTCEA DTCEB DTCEC DTCED DTCEE DTCEF DTVECR SBYCR SYSCR SCKCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 SWDTE SSBY -- PSTOP DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 STS2 -- -- STS1 INTM1 -- STS0 INTM0 -- OPE NMIEG -- -- -- SCK2 -- -- SCK1 -- RAME SCK0 Power8 down state MCU Clock pulse generator MCU 8 8 H'FF3B H'FF3C H'FF3D H'FF44 MDCR -- -- -- -- -- MDS2 MDS1 MDS0 MSTP8 MSTP0 -- 8 MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 LPWCR -- MSTP6 -- MSTP5 RFCUT MSTP4 -- MSTP3 -- MSTP2 -- MSTP1 -- Power8 down state Clock pulse generator Port 1 Port 2 Port 3 Port 4 Port 5 Port A Port B Port C Port D Port E Port F Port G Port 1 Port 2 8 H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 PORT1 PORT2 PORT3 PORT4 PORT5 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P17 P27 -- -- -- -- PB7 PC7 PD7 PE7 PF7 -- P17DR P27DR P16 P26 -- -- -- -- PB6 PC6 PD6 PE6 PF6 -- P16DR P26DR P15 P25 P35 -- -- -- PB5 PC5 PD5 PE5 PF5 -- P15DR P25DR P14 P24 P34 -- -- -- PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P13 P23 P33 P43 P53 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P12 P22 P32 P42 P52 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P11 P21 P31 P41 P51 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P10 P20 P30 P40 P50 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR 8 Rev.3.00 Mar. 26, 2007 Page 639 of 772 REJ09B0355-0300 Appendix B Register Field Bus Width (Bit) 8 Address Register (Low) Name H'FF62 H'FF64 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 H'FF78 P3DR P5DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR SMR0 SMR0 H'FF79 BRR0 Bit 7 -- -- -- PB7DR PC7DR PD7DR PE7DR PF7DR -- -- Bit 6 -- -- -- PB6DR PC6DR PD6DR PE6DR PF6DR -- -- Bit 5 P35DR -- -- PB5DR PC5DR PD5DR PE5DR PF5DR -- -- Bit 4 P34DR -- -- PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR -- Bit 3 P33DR P53DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR Bit 2 P32DR P52DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR Bit 1 P31DR P51DR PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR Bit 0 P30DR P50DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR PG0DR Module Name Port 3 Port 5 Port A Port B Port C Port D Port E Port F Port G PA3PCR PA2PCR PA1PCR PA0PCR Port A PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Port B PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Port C PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Port D PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Port E -- -- C/A GM -- -- CHR CHR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Port 3 -- PE PE -- O/E O/E PA3ODR PA2ODR PA1ODR PA0ODR Port A STOP STOP MP MP CKS1 CKS1 CKS0 CKS0 SCI0 Smart card interface 0 SCI0, Smart card interface 0 TIE TIE RIE RIE TE TE RE RE MPIE MPIE TEIE TEIE CKE1 CKE1 CKE0 CKE0 SCI0, Smart card interface 0 SCI0 Smart card interface 0 SCI0, Smart card interface 0 8 H'FF7A SCR0 SCR0 H'FF7B H'FF7C TDR0 SSR0 SSR0 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT H'FF7D H'FF7E RDR0 SCMR0 -- -- -- -- SDIR SINV -- SMIF Rev.3.00 Mar. 26, 2007 Page 640 of 772 REJ09B0355-0300 Appendix B Register Field Bus Width (Bit) 8 Address Register (Low) Name H'FF80 SMR1 SMR1 H'FF81 BRR1 Bit 7 C/A GM Bit 6 CHR CHR Bit 5 PE PE Bit 4 O/E O/E Bit 3 STOP STOP Bit 2 MP MP Bit 1 CKS1 CKS1 Bit 0 CKS0 CKS0 Module Name SCI1 Smart card interface 1 SCI1, Smart card interface 1 H'FF82 SCR1 SCR1 TIE TIE RIE RIE TE TE RE RE MPIE MPIE TEIE TEIE CKE1 CKE1 CKE0 CKE0 SCI1, Smart card interface 1 SCI1 Smart card interface 1 SCI1, Smart card interface 1 SCI2 Smart card interface 2 SCI2, Smart card interface 2 H'FF83 H'FF84 TDR1 SSR1 SSR1 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT H'FF85 H'FF86 H'FF88 RDR1 SCMR1 SMR2 SMR2 -- C/A GM -- CHR CHR -- PE PE -- O/E O/E SDIR STOP STOP SINV MP MP -- CKS1 CKS1 SMIF CKS0 CKS0 H'FF89 BRR2 H'FF8A SCR2 SCR2 TIE TIE RIE RIE TE TE RE RE MPIE MPIE TEIE TEIE CKE1 CKE1 CKE0 CKE0 SCI2, Smart card interface 2 SCI2 Smart card interface 2 SCI2, Smart card interface 2 A/D converter 8 H'FF8B H'FF8C TDR2 SSR2 SSR2 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 RDR2 SCMR2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL -- AD9 AD1 AD9 AD1 AD9 AD1 -- AD8 AD0 AD8 AD0 AD8 AD0 -- AD7 -- AD7 -- AD7 -- -- AD6 -- AD6 -- AD6 -- SDIR AD5 -- AD5 -- AD5 -- SINV AD4 -- AD4 -- AD4 -- -- AD3 -- AD3 -- AD3 -- SMIF AD2 -- AD2 -- AD2 -- Rev.3.00 Mar. 26, 2007 Page 641 of 772 REJ09B0355-0300 Appendix B Register Field Bus Width (Bit) 8 Address Register (Low) Name H'FF96 H'FF97 H'FF98 H'FF99 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBC (write) H'FFBC (read) H'FFBC (write) H'FFBD (read) H'FFBE (write) H'FFBF (read) ADDRDH ADDRDL ADCSR ADCR TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 TCSR Bit 7 AD9 AD1 ADF TRGS1 CMIEB CMIEB CMFB CMFB Bit 6 AD8 AD0 ADIE TRGS0 CMIEA CMIEA CMFA CMFA Bit 5 AD7 -- ADST -- OVIE OVIE OVF OVF Bit 4 AD6 -- SCAN -- CCLR1 CCLR1 ADTE -- Bit 3 AD5 -- CKS -- CCLR0 CCLR0 OS3 OS3 Bit 2 AD4 -- -- -- CKS2 CKS2 OS2 OS2 Bit 1 AD3 -- CH1 -- CKS1 CKS1 OS1 OS1 Bit 0 AD2 -- CH0 -- CKS0 CKS0 OS0 OS0 Module Name A/D converter 8-bit timer channel 0 8-bit timer channel 1 8-bit timer channel 0 8-bit timer channel 1 8-bit timer channel 0 8-bit timer channel 1 8-bit timer channel 0 8-bit timer channel 1 8-bit timer channel 0 8-bit timer channel 1 16 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 WDT 16 TCNT WDT RSTCSR WOVF RSTE RSTS -- -- -- -- -- WDT Rev.3.00 Mar. 26, 2007 Page 642 of 772 REJ09B0355-0300 Appendix B Register Field Bus Width (Bit) 16 Address Register (Low) Name H'FFC0 H'FFC1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA TSTR TSYR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B Bit 7 -- -- CCLR2 -- IOB3 IOD3 TTGE -- Bit 6 -- -- CCLR1 -- IOB2 IOD2 -- -- Bit 5 -- -- CCLR0 BFB IOB1 IOD1 -- -- Bit 4 -- -- CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 -- -- CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module Name TPU TPU0 16 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 16 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 16 Note: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. Rev.3.00 Mar. 26, 2007 Page 643 of 772 REJ09B0355-0300 Appendix B Register Field B.2 Register Descriptions H'F800--H'FBFF 5 DM1 -- 4 DM0 -- 3 MD1 -- 2 MD0 -- 1 DTS -- 0 Sz -- MRA--DTC Mode Register A Bit : 7 SM1 Initial value : Read/Write : -- 6 SM0 -- DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 -- 0 1 Source Address Mode 0 1 -- 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode -- Destination side is repeat area or block area Source side is repeat area or block area Rev.3.00 Mar. 26, 2007 Page 644 of 772 REJ09B0355-0300 Appendix B Register Field MRB--DTC Mode Register B Bit : 7 CHNE Initial value : Read/Write : -- 6 DISEL -- 5 -- -- 4 -- -- H'F800--H'FBFF 3 -- -- 2 -- -- 1 -- -- 0 DTC -- -- Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Interrupt Select 0 1 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 1 End of DTC data transfer DTC chain transfer SAR--DTC Source Address Register Bit : 23 22 21 20 19 H'F800--H'FBFF --------4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies transfer data source address DAR--DTC Destination Address Register Bit : 23 22 21 20 19 H'F800--H'FBFF --------4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies transfer data destination address Rev.3.00 Mar. 26, 2007 Page 645 of 772 REJ09B0355-0300 Appendix B Register Field CRA--DTC Transfer Count Register A Bit : 15 14 13 12 11 10 9 8 H'F800--H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CRAH CRAL Specifies the number of DTC data transfers CRB--DTC Transfer Count Register B Bit : 15 14 13 12 11 10 9 8 H'F800--H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Specifies the number of DTC block data transfers P1DDR--Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB0 3 0 W 2 0 W 1 0 W Port 1 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : Specify input or output for individual port 1 pins Rev.3.00 Mar. 26, 2007 Page 646 of 772 REJ09B0355-0300 Appendix B Register Field P2DDR--Port 2 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB1 3 0 W 2 0 W 1 0 W Port 2 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : Specify input or output for individual port 2 pins P3DDR--Port 3 Data Direction Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 W 4 0 W H'FEB2 3 0 W 2 0 W 1 0 W Port 3 0 0 W P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined Specify input or output for individual port 3 pins P5DDR--Port 5 Data Direction Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FEB4 3 0 W 2 0 W 1 0 W 0 0 W Port 5 P53DDR P52DDR P51DDR P50DDR Undefined Undefined Undefined Undefined Specify input or output for individual port 5 pins Rev.3.00 Mar. 26, 2007 Page 647 of 772 REJ09B0355-0300 Appendix B Register Field PADDR--Port A Data Direction Register Bit Initial value Read/Write : : : 7 -- -- 6 -- -- 5 -- -- 4 -- -- H'FEB9 3 0 W 2 0 W 1 0 W Port A 0 0 W PA3DDR PA2DDR PA1DDR PA0DDR Undefined Undefined Undefined Undefined Specify input or output for individual port A pins PBDDR--Port B Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBA 3 0 W 2 0 W 1 0 W Port B 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Specify input or output for individual port B pins PCDDR--Port C Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBB 3 0 W 2 0 W 1 0 W Port C 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Specify input or output for individual port C pins Rev.3.00 Mar. 26, 2007 Page 648 of 772 REJ09B0355-0300 Appendix B Register Field PDDDR--Port D Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBC 3 0 W 2 0 W 1 0 W Port D 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write : Specify input or output for individual port D pins PEDDR--Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBD 3 0 W 2 0 W 1 0 W Port E 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : Specify input or output for individual port E pins PFDDR--Port F Data Direction Register Bit : 7 6 5 H'FEBE 4 3 2 1 Port F 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4, 5, 6 Initial value Read/Write Modes 3, 7 Initial value Read/Write : : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for individual port F pins Rev.3.00 Mar. 26, 2007 Page 649 of 772 REJ09B0355-0300 Appendix B Register Field PGDDR--Port G Data Direction Register Bit Modes 1, 4, 5 Initial value Read/Write Initial value Read/Write : Undefined Undefined Undefined : -- -- -- 1 W 0 W : 7 -- 6 -- 5 -- 4 H'FEBF 3 2 1 Port G 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 2, 3, 6, 7 : Undefined Undefined Undefined : -- -- -- Specify input or output for individual port G pins ICRA--Interrupt Control Register A ICRB--Interrupt Control Register B ICRC--Interrupt Control Register C Bit : 7 ICR7 Initial value : Read/Write : 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W H'FEC0 H'FEC1 H'FEC2 3 ICR3 0 R/W 2 ICR2 0 R/W Interrupt Controller Interrupt Controller Interrupt Controller 1 ICR1 0 R/W 0 ICR0 0 R/W Sets the interrupt control level for interrupts Correspondence between Interrupt Sources and ICR Settings Bits Register ICRA 7 IRQ0 6 IRQ1 5 IRQ2 IRQ3 4 IRQ4 IRQ5 3 IRQ6 IRQ7 2 DTC 1 Watchdog -- timer -- -- 0 ICRB -- TPU TPU A/D TPU -- converter channel 0 channel 1 channel 2 ICRC 8-bit 8-bit -- timer timer channel 0 channel 1 SCI SCI SCI -- channel 0 channel 1 channel 2 -- Rev.3.00 Mar. 26, 2007 Page 650 of 772 REJ09B0355-0300 Appendix B Register Field ABWCR--Bus Width Control Register Bit : 7 ABW7 Modes 1, 2, 3, 5, 6, 7 Initial value Read/Write Mode 4 Initial value Read/Write : : 0 R/W 0 R/W 0 R/W 0 : : 1 R/W 1 R/W 1 R/W 1 6 ABW6 5 ABW5 4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W Bus Controller 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W ABW4 R/W R/W Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access Note: n = 7 to 0 ASTCR--Access State Control Register Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled. 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled Note: n = 7 to 0 Rev.3.00 Mar. 26, 2007 Page 651 of 772 REJ09B0355-0300 Appendix B Register Field WCRH--Wait Control Register H Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 H'FED2 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bus Controller W51 1 R/W Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev.3.00 Mar. 26, 2007 Page 652 of 772 REJ09B0355-0300 Appendix B Register Field WCRL--Wait Control Register L Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 H'FED3 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bus Controller W11 1 R/W Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev.3.00 Mar. 26, 2007 Page 653 of 772 REJ09B0355-0300 Appendix B Register Field BCRH--Bus Control Register H Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 -- 0 R/W 1 -- 0 R/W Bus Controller 0 -- 0 R/W BRSTRM BRSTS1 BRSTS0 Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Area 0 Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas Rev.3.00 Mar. 26, 2007 Page 654 of 772 REJ09B0355-0300 Appendix B Register Field BCRL--Bus Control Register L Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 -- 1 R/W H'FED5 3 -- 1 R/W 2 ASS 1 R/W 1 -- 0 R/W Bus Controller 0 WAITE 0 R/W WAIT Pin Enable 0 Wait input by WAIT pin disabled Wait input by WAIT pin enabled 1 Area Partition Unit Select 0 1 Area partition unit is 128 kbytes (1 Mbit) Area partition unit is 2 Mbytes (16 Mbits) External Addresses H'010000 to H'01FFFF Enable 0 1 On-chip ROM (H8S/2246 and H8S/2245) or a reserved area (H8S/2244, H8S/2243, H8S/2242, and H8S/2241) External addresses (in external expansion mode) or reserved area* (in single-chip mode) Note: * Do not access a reserved area. BREQO Pin Enable 0 1 BREQO output disabled BREQO output enabled Bus Release Enable 0 1 External bus release is disabled External bus release is enabled Rev.3.00 Mar. 26, 2007 Page 655 of 772 REJ09B0355-0300 Appendix B Register Field ISCRH--IRQ Sense Control Register H ISCRL--IRQ Sense Control Register L ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W H'FF2C H'FF2D Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write : IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write : IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Note: n = 7 to 0 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input Rev.3.00 Mar. 26, 2007 Page 656 of 772 REJ09B0355-0300 Appendix B Register Field IER--IRQ Enable Register Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 H'FF2E 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ4E 0 R/W IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled Note: n = 7 to 0 ISR--IRQ Status Register Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 H'FF2F 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ4F 0 R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 657 of 772 REJ09B0355-0300 Appendix B Register Field DTCER--DTC Enable Registers Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 H'FF30 to H'FF35 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC DTCE4 0 R/W DTCE0 0 R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 Correspondence between interrupt sources and DTCER bits Register 7 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF IRQ0 -- TGI2A -- -- RXI2 6 IRQ1 ADI TGI2B -- -- TXI2 5 IRQ2 TGI0A -- -- -- -- 4 IRQ3 TGI0B -- -- -- -- Bit 3 IRQ4 TGI0C -- RXI0 -- 2 IRQ5 TGI0D -- TXI0 -- 1 IRQ6 TGI1A -- RXI1 -- 0 IRQ7 TGI1B -- TXI1 -- CMIA0 CMIB0 CMIA1 CMIB1 Rev.3.00 Mar. 26, 2007 Page 658 of 772 REJ09B0355-0300 Appendix B Register Field DTVECR--DTC Vector Register Bit : 7 0 R/(W)*1 6 0 5 4 H'FF37 3 2 1 0 DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : 0 0 0 0 0 0 *2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W) Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not ended * When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. DTC software activation is enabled [Holding conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended * During data transfer activated by software 1 Notes: 1. A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. 2. Only write to bits DTVEC6 to DTVEC0 when SWDTE is 0. Rev.3.00 Mar. 26, 2007 Page 659 of 772 REJ09B0355-0300 Appendix B Register Field SBYCR--Standby Control Register Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W H'FF38 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Power-Down State Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state 1 Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Rev.3.00 Mar. 26, 2007 Page 660 of 772 REJ09B0355-0300 Appendix B Register Field SYSCR--System Control Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W H'FF39 3 NMIEG 0 R/W 2 -- 0 -- RAM Enable* 0 1 1 -- 0 -- 0 MCU RAME 1 R/W On-chip RAM disabled On-chip RAM enabled Note: * When the DTC is used, the RAME bit should not be cleared to 0. NMI Input Edge Select 0 1 Falling edge Rising edge Interrupt Control Mode Selection 0 0 1 1 0 1 Interrupt control mode 0 Interrupt control mode 1 Setting prohibited Setting prohibited Rev.3.00 Mar. 26, 2007 Page 661 of 772 REJ09B0355-0300 Appendix B Register Field SCKCR--System Clock Control Register Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- H'FF3A 2 SCK2 0 R/W 1 SCK1 0 R/W Clock Pulse Generator 0 SCK0 0 R/W Bus Master Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 Clock Output Control PSTOP 0 1 Normal Operation output Fixed high Sleep Mode output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance -- Bus master is in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- MDCR--Mode Control Register Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FF3B 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MCU MDS0 --* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 Rev.3.00 Mar. 26, 2007 Page 662 of 772 REJ09B0355-0300 Appendix B Register Field MSTPCRH--Module Stop Control Register H MSTPCRL--Module Stop Control Register L MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 H'FF3C H'FF3D Power-Down State Power-Down State MSTPCRL 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set LPWCR--Low Power Control Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 RFCUT 0 R/W 4 -- 0 R/W H'FF44 3 -- 0 R/W 2 -- 0 R/W Clock Oscillator 1 -- 0 R/W 0 -- 0 R/W Control of Oscillator's Built-In Feedback Resistor in External Clock Input 0 1 Oscillator's built-in feedback resistor and duty adjustment circuit are used Oscillator's built-in feedback resistor and duty adjustment circuit are not used Rev.3.00 Mar. 26, 2007 Page 663 of 772 REJ09B0355-0300 Appendix B Register Field PORT1--Port 1 Register Bit : 7 P17 Initial value : Read/Write : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R H'FF50 3 P13 --* R 2 P12 --* R 1 P11 --* R Port 1 0 P10 --* R State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT2--Port 2 Register Bit : 7 P27 Initial value : Read/Write : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R H'FF51 3 P23 --* R 2 P22 --* R 1 P21 --* R Port 2 0 P20 --* R State of port 2 pins Note: * Determined by the state of pins P27 to P20. PORT3--Port 3 Register Bit : 7 -- Read/Write : -- 6 -- -- 5 P35 --* R 4 P34 --* R H'FF52 3 P33 --* R 2 P32 --* R 1 P31 --* R Port 3 0 P30 --* R Initial value : Undefined Undefined State of port 3 pins Note: * Determined by the state of pins P35 to P30. Rev.3.00 Mar. 26, 2007 Page 664 of 772 REJ09B0355-0300 Appendix B Register Field PORT4--Port 4 Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF53 3 P43 --* R 2 P42 --* R 1 P41 --* R Port 4 0 P40 --* R Initial value : Undefined Undefined Undefined Undefined State of port 4 pins Note: * Determined by the state of pins P43 to P40. PORT5--Port 5 Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF54 3 P53 --* R 2 P52 --* R 1 P51 --* R Port 5 0 P50 --* R Undefined Undefined Undefined Undefined State of port 5 pins Note: * Determined by the state of pins P53 to P50. PORTA--Port A Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF59 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R Port A 0 PA0 --* R Undefined Undefined Undefined Undefined State of port A pins Note: * Determined by the state of pins PA3 to PA0. Rev.3.00 Mar. 26, 2007 Page 665 of 772 REJ09B0355-0300 Appendix B Register Field PORTB--Port B Register Bit : 7 PB7 Initial value : Read/Write : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R H'FF5A 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R Port B 0 PB0 --* R State of port B pins Note: * Determined by the state of pins PB7 to PB0. PORTC--Port C Register Bit : 7 PC7 Initial value : Read/Write : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R H'FF5B 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R Port C 0 PC0 --* R State of port C pins Note: * Determined by the state of pins PC7 to PC0. PORTD--Port D Register Bit : 7 PD7 Initial value : Read/Write : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R H'FF5C 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R Port D 0 PD0 --* R State of port D pins Note: * Determined by the state of pins PD7 to PD0. Rev.3.00 Mar. 26, 2007 Page 666 of 772 REJ09B0355-0300 Appendix B Register Field PORTE--Port E Register Bit : 7 PE7 Initial value : Read/Write : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R H'FF5D 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R Port E 0 PE0 --* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF--Port F Register Bit : 7 PF7 Initial value : Read/Write : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R H'FF5E 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R Port F 0 PF0 --* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. PORTG--Port G Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 PG4 --* R H'FF5F 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R Port G 0 PG0 --* R Initial value : Undefined Undefined Undefined State of port G pins Note: * Determined by the state of pins PG4 to PG0. Rev.3.00 Mar. 26, 2007 Page 667 of 772 REJ09B0355-0300 Appendix B Register Field P1DR--Port 1 Data Register Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 H'FF60 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W Port 1 0 P10DR 0 R/W P14DR 0 R/W Stores output data for port 1 pins (P17 to P10) P2DR--Port 2 Data Register Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 H'FF61 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W Port 2 0 P20DR 0 R/W P24DR 0 R/W Stores output data for port 2 pins (P27 to P20) P3DR--Port 3 Data Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 P35DR 0 R/W 4 H'FF62 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W Port 3 0 P30DR 0 R/W P34DR 0 R/W Undefined Undefined Stores output data for port 3 pins (P35 to P30) Rev.3.00 Mar. 26, 2007 Page 668 of 772 REJ09B0355-0300 Appendix B Register Field P5DR--Port 5 Data Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF64 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 Port 5 P50DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for port 5 pins (P53 to P50) PADR--Port A Data Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF69 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 Port A PA0DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for port A pins (PA3 to PA0) PBDR--Port B Data Register Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 H'FF6A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W Port B 0 PB0DR 0 R/W PB4DR 0 R/W Stores output data for port B pins (PB7 to PB0) Rev.3.00 Mar. 26, 2007 Page 669 of 772 REJ09B0355-0300 Appendix B Register Field PCDR--Port C Data Register Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 H'FF6B 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W Port C 0 PC0DR 0 R/W PC4DR 0 R/W Stores output data for port C pins (PC7 to PC0) PDDR--Port D Data Register Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 H'FF6C 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W Port D 0 PD0DR 0 R/W PD4DR 0 R/W Stores output data for port D pins (PD7 to PD0) PEDR--Port E Data Register Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 H'FF6D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W Port E 0 PE0DR 0 R/W PE4DR 0 R/W Stores output data for port E pins (PE7 to PE0) Rev.3.00 Mar. 26, 2007 Page 670 of 772 REJ09B0355-0300 Appendix B Register Field PFDR--Port F Data Register Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 H'FF6E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W Port F 0 PF0DR 0 R/W PF4DR 0 R/W Stores output data for port F pins (PF7 to PF0) PGDR--Port G Data Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 0 R/W H'FF6F 3 0 R/W 2 0 R/W 1 0 R/W Port G 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined Stores output data for port G pins (PG4 to PG0) PAPCR--Port A MOS Pull-Up Control Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF70 3 0 R/W 2 0 R/W 1 0 R/W Port A 0 0 R/W PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Undefined Undefined Undefined Undefined Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis Rev.3.00 Mar. 26, 2007 Page 671 of 772 REJ09B0355-0300 Appendix B Register Field PBPCR--Port B MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF71 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port B PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis PCPCR--Port C MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF72 3 0 R/W 2 0 R/W 1 0 R/W Port C 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis PDPCR--Port D MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF73 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port D PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis Rev.3.00 Mar. 26, 2007 Page 672 of 772 REJ09B0355-0300 Appendix B Register Field PEPCR--Port E MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF74 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port E PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis P3ODR--Port 3 Open Drain Control Register Bit : 7 -- Read/Write : -- 6 -- -- 5 0 R/W 4 0 R/W H'FF76 3 0 R/W 2 0 R/W 1 0 R/W Port 3 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : Undefined Undefined Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR--Port A Open Drain Control Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF77 3 0 R/W 2 0 R/W 1 0 R/W Port A 0 0 R/W PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Undefined Undefined Undefined Undefined Controls the PMOS on/off status for each port A pin (PA3 to PA0) Rev.3.00 Mar. 26, 2007 Page 673 of 772 REJ09B0355-0300 Appendix B Register Field SMR0--Serial Mode Register 0 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI0 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.3.00 Mar. 26, 2007 Page 674 of 772 REJ09B0355-0300 Appendix B Register Field SMR0--Serial Mode Register 0 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 0 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Interval for transfer of one bit Rev.3.00 Mar. 26, 2007 Page 675 of 772 REJ09B0355-0300 Appendix B Register Field BRR0--Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details. Rev.3.00 Mar. 26, 2007 Page 676 of 772 REJ09B0355-0300 Appendix B Register Field SCR0--Serial Control Register 0 Bit : H'FF7A 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode SCI0 0 CKE0 0 R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W Initial value : Read/Write : Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.3.00 Mar. 26, 2007 Page 677 of 772 REJ09B0355-0300 Appendix B Register Field SCR0--Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 0 SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.3.00 Mar. 26, 2007 Page 678 of 772 REJ09B0355-0300 Appendix B Register Field TDR0--Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF7B 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev.3.00 Mar. 26, 2007 Page 679 of 772 REJ09B0355-0300 Appendix B Register Field SSR0--Serial Status Register 0 Bit : 7 TDRE 1 R/(W)*1 6 RDRF 5 ORER 4 FER 3 PER 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W SCI0 Initial value : Read/Write : 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC*2 is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 680 of 772 REJ09B0355-0300 Appendix B Register Field SSR0--Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 ERS 0 3 PER 0 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Smart Card Interface 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 1 Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC*2 is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 681 of 772 REJ09B0355-0300 Appendix B Register Field RDR0--Receive Data Register 0 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D 3 0 R SCI0, Smart Card Interface 0 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR0--Smart Card Mode Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W H'FF7E 2 SINV 0 R/W SCI0, Smart Card Interface 0 1 -- 1 -- 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.3.00 Mar. 26, 2007 Page 682 of 772 REJ09B0355-0300 Appendix B Register Field SMR1--Serial Mode Register 1 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI1 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.3.00 Mar. 26, 2007 Page 683 of 772 REJ09B0355-0300 Appendix B Register Field SMR1--Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 1 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Interval for transfer of one bit Rev.3.00 Mar. 26, 2007 Page 684 of 772 REJ09B0355-0300 Appendix B Register Field BRR1--Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF81 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details. Rev.3.00 Mar. 26, 2007 Page 685 of 772 REJ09B0355-0300 Appendix B Register Field SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI1 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.3.00 Mar. 26, 2007 Page 686 of 772 REJ09B0355-0300 Appendix B Register Field SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 1 SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.3.00 Mar. 26, 2007 Page 687 of 772 REJ09B0355-0300 Appendix B Register Field TDR1--Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF83 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev.3.00 Mar. 26, 2007 Page 688 of 772 REJ09B0355-0300 Appendix B Register Field SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 5 ORER 4 FER 3 PER 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted SCI1 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC*2 is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 689 of 772 REJ09B0355-0300 Appendix B Register Field SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 5 ORER 4 ERS 3 PER 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Smart Card Interface 1 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR 1 [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR 1 Error Signal Status 0 [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 1 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC*2 is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 690 of 772 REJ09B0355-0300 Appendix B Register Field RDR1--Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF85 3 0 R SCI1, Smart Card Interface 1 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR1--Smart Card Mode Register 1 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'FF86 2 SINV 0 R/W SCI1, Smart Card Interface 1 1 -- 1 -- 0 SMIF 0 R/W SDIR 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.3.00 Mar. 26, 2007 Page 691 of 772 REJ09B0355-0300 Appendix B Register Field SMR2--Serial Mode Register 2 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI2 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.3.00 Mar. 26, 2007 Page 692 of 772 REJ09B0355-0300 Appendix B Register Field SMR2--Serial Mode Register 2 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 2 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Interval for transfer of one bit Rev.3.00 Mar. 26, 2007 Page 693 of 772 REJ09B0355-0300 Appendix B Register Field BRR2--Bit Rate Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF89 3 1 R/W SCI2, Smart Card Interface 2 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details. Rev.3.00 Mar. 26, 2007 Page 694 of 772 REJ09B0355-0300 Appendix B Register Field SCR2--Serial Control Register 2 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF8A 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI2 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.3.00 Mar. 26, 2007 Page 695 of 772 REJ09B0355-0300 Appendix B Register Field SCR2--Serial Control Register 2 Bit : H'FF8A 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 2 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W Initial value : Read/Write : SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.3.00 Mar. 26, 2007 Page 696 of 772 REJ09B0355-0300 Appendix B Register Field TDR2--Transmit Data Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF8B 3 1 R/W SCI2, Smart Card Interface 2 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev.3.00 Mar. 26, 2007 Page 697 of 772 REJ09B0355-0300 Appendix B Register Field SSR2--Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 5 ORER 4 FER 3 PER 2 TEND 1 R H'FF8C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted SCI2 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC*2 is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 698 of 772 REJ09B0355-0300 Appendix B Register Field SSR2--Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 ERS 0 3 PER 0 2 TEND 1 R H'FF8C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Smart Card Interface 2 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] On of the next serial reception when RDRF = 1 completion Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC*2 is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC*2 is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 699 of 772 REJ09B0355-0300 Appendix B Register Field RDR2--Receive Data Register 2 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF8D 3 0 R SCI2, Smart Card Interface 2 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR2--Smart Card Mode Register 2 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W H'FF8E 2 SINV 0 R/W SCI2, Smart Card Interface 2 1 -- 1 -- 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.3.00 Mar. 26, 2007 Page 700 of 772 REJ09B0355-0300 Appendix B Register Field ADDRAH--A/D Data Register AH ADDRAL--A/D Data Register AL ADDRBH--A/D Data Register BH ADDRBL--A/D Data Register BL ADDRCH--A/D Data Register CH ADDRCL--A/D Data Register CL ADDRDH--A/D Data Register DH ADDRDL--A/D Data Register DL Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : Read/Write : Stores the results of A/D conversion Analog Input Channel AN0 AN1 AN2 AN3 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.3.00 Mar. 26, 2007 Page 701 of 772 REJ09B0355-0300 Appendix B Register Field ADCSR--A/D Control/Status Register Bit : 7 ADF Initial value : Read/Write : 0 R/(W)*1 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 H'FF98 2 -- 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W A/D Converter CKS 0 R/W Channel Select CH1 CH0 0 0 1 1 0 1 Group Select 0 1 Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode Single mode Scan mode Conversion time= 266 states (max.) Conversion time= 134 states (max.) Single Mode Scan Mode (SCAN = 0) (SCAN = 1) AN0 AN1 AN2 AN3 AN0 AN0 to AN1 AN0 to AN2 AN0 to AN3 A/D Interrupt Enable 0 1 A/D End Flag 0 [Clearing conditions] * When 0 is written to the ADF flag after reading ADF = 1 * When the DTC*2 is activated by an ADI interrupt, and ADDR is read [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When one round of conversion has been performed on all specified channels A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled 1 Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 702 of 772 REJ09B0355-0300 Appendix B Register Field ADCR--A/D Control Register Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- H'FF99 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- A/D Timer Trigger Select TRGS1 0 TRGS1 0 Description Start of A/D conversion by external trigger is disabled Start of A/D conversion by external trigger (TPU) is enabled Start of A/D conversion by external trigger (8-bit timer) is enabled Start of A/D conversion by external trigger pin is enabled 1 1 0 1 Rev.3.00 Mar. 26, 2007 Page 703 of 772 REJ09B0355-0300 Appendix B Register Field TCR0--Time Control Register 0 TCR1--Time Control Register 1 Bit : 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 H'FFB0 H'FFB1 1 CKS1 0 R/W 0 CKS0 0 R/W 8-Bit Timer Channel 0 8-Bit Timer Channel 1 CKS2 0 R/W Initial value : Read/Write : Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of /8 Internal clock: counted at falling edge of /64 Internal clock: counted at falling edge of /8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges 1 1 0 1 Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled Rev.3.00 Mar. 26, 2007 Page 704 of 772 REJ09B0355-0300 Appendix B Register Field TCSR0--Timer Control/Status Register 0 TCSR1--Timer Control/Status Register 1 TCSR0 Bit : 7 CMFB 0 6 CMFA 0 5 OVF 0 4 ADTE 0 R/W 4 -- 1 -- 3 H'FFB2 H'FFB3 2 OS2 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 1 OS1 0 R/W OS3 0 R/W 3 OS3 0 R/W 8-Bit Timer Channel 0 8-Bit Timer Channel 1 0 OS0 0 R/W 0 OS0 0 R/W Initial value : Read/Write : R/(W)*1 R/(W)*1 R/(W)*1 TCSR1 Bit : 7 CMFB 6 CMFA 5 OVF 0 0 0 Initial value : Read/Write : R/(W)*1 R/(W)*1 R/(W)*1 Output Select 0 0 1 1 0 1 Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) Compare Match Flag A 0 [Clearing conditions] * Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA * When the DTC*2 is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORA 1 Compare Match Flag B 0 [Clearing conditions] * Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB * When the DTC*2 is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORB 1 Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 705 of 772 REJ09B0355-0300 Appendix B Register Field TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1 TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1 TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORB1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0--Timer Counter 0 TCNT1--Timer Counter 1 TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFB8 H'FFB9 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCNT1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.3.00 Mar. 26, 2007 Page 706 of 772 REJ09B0355-0300 Appendix B Register Field TCSR--Timer Control/Status Register Bit : 7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- H'FFBC (W) H'FFBC (R) 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W WDT Initial value : 0 Read/Write : R/(W)*1 Clock Select CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Overflow period* (when = 20 MHz) 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s /2 (initial value) 25.6 s /64 /128 /512 /2048 /8192 /32768 /131072 Timer Enable 0 1 Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF*2 [Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows Notes: The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. 1. Can only be written with 0 for flag clearing. 2. When polling OVF with the interval timer interrupt disabled, read TSCR twice or more while OVF is set to 1. Rev.3.00 Mar. 26, 2007 Page 707 of 772 REJ09B0355-0300 Appendix B Register Field TCNT--Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFBC (W) H'FFBD (R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT Initial value : Read/Write : R/W Note: The method for writing to TCNT is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. Rev.3.00 Mar. 26, 2007 Page 708 of 772 REJ09B0355-0300 Appendix B Register Field RSTCSR--Reset Control/Status Register Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- H'FFBE (W) H'FFBF (R) 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 WDT -- 1 -- Reset Select 0 1 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Power-on reset Manual reset Note: * The modules H8S/2245 Group are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Notes: The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. * Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 709 of 772 REJ09B0355-0300 Appendix B Register Field TSTR--Timer Start Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FFC0 3 -- 0 -- 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W TPU Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation Note: n = 2 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. TSYR--Timer Synchro Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FFC1 3 -- 0 -- 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 TPU SYNC0 0 R/W Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Note: n = 2 to 0 Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev.3.00 Mar. 26, 2007 Page 710 of 772 REJ09B0355-0300 Appendix B Register Field TCR0--Timer Control Register 0 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFD0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU0 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation TCNT clearing disabled TCNT cleared by TGRC compare match/input capture TCNT cleared by TGRD compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation -- Count at rising edge Count at falling edge Count at both edges Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Rev.3.00 Mar. 26, 2007 Page 711 of 772 REJ09B0355-0300 Appendix B Register Field TMDR0--Timer Mode Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W H'FFD1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 TPU0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- Legend: *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Buffer Operation Setting A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation Setting B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev.3.00 Mar. 26, 2007 Page 712 of 772 REJ09B0355-0300 Appendix B Register Field TIOR0H--Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W H'FFD2 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU0 TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 TGR0B I/O Control 0 * Setting prohibited Legend: *: Don't care 0 0 0 1 1 0 1 TGR0B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 0 1 1 0 0 0 1 1 * * 1 * Setting prohibited Legend: *: Don't care Rev.3.00 Mar. 26, 2007 Page 713 of 772 REJ09B0355-0300 Appendix B Register Field TIOR0L--Timer I/O Control Register 0L Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W H'FFD3 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 0 TGR0C Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0C Capture input is input source is 1 capture TIOCC0 pin register*1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * Setting prohibited Legend: *: Don't care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0 0 0 0 TGR0D Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0D Capture input is input source is 1 capture TIOCD0 pin 1 * * register * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * Setting prohibited Legend: *: Don't care Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev.3.00 Mar. 26, 2007 Page 714 of 772 REJ09B0355-0300 Appendix B Register Field TIER0--Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 H'FFD4 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU0 TGIED 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.3.00 Mar. 26, 2007 Page 715 of 772 REJ09B0355-0300 Appendix B Register Field TSR0--Timer Status Register 0 Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 3 TGFD 2 TGFC 1 H'FFD5 0 TGFA TGFB TPU0 Initial value : Read/Write : 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 0 0 R/(W)*1 R/(W)*1 TGRA*Input Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0. * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 TGRB*Input Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0. * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 TGRC*Input Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 TGRD*Input Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 716 of 772 REJ09B0355-0300 Appendix B Register Field TCNT0--Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FFD6 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFD8 H'FFDA H'FFDC H'FFDE 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.3.00 Mar. 26, 2007 Page 717 of 772 REJ09B0355-0300 Appendix B Register Field TCR1--Timer Control Register 1 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFE0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU1 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Setting prohibited Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 1 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation Rev.3.00 Mar. 26, 2007 Page 718 of 772 REJ09B0355-0300 Appendix B Register Field TMDR1--Timer Mode Register 1 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FFE1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 TPU1 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- Legend: *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.3.00 Mar. 26, 2007 Page 719 of 772 REJ09B0355-0300 Appendix B Register Field TIOR1--Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W H'FFE2 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU1 TGR1A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is input capture register Capture input source is TIOCA1 pin Setting prohibited TGR1A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: *: Don't care TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Setting prohibited TGR1B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: *: Don't care Rev.3.00 Mar. 26, 2007 Page 720 of 772 REJ09B0355-0300 Appendix B Register Field TIER1--Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- H'FFE4 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A TPU1 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.3.00 Mar. 26, 2007 Page 721 of 772 REJ09B0355-0300 Appendix B Register Field TSR1--Timer Status Register 1 Bit : 7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 4 TCFV 0 3 -- 0 -- 2 -- 0 -- H'FFE5 1 TGFB 0 0 TGFA 0 TPU1 Initial value : Read/Write : R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 TGRA Input Capture/Output Compare Flag 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC*2 is 0. * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 TGRB Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0. * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 722 of 772 REJ09B0355-0300 Appendix B Register Field TCNT1--Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFE6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFE8 H'FFEA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 TPU1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.3.00 Mar. 26, 2007 Page 723 of 772 REJ09B0355-0300 Appendix B Register Field TCR2--Timer Control Register 2 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFF0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU2 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 2 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation Rev.3.00 Mar. 26, 2007 Page 724 of 772 REJ09B0355-0300 Appendix B Register Field TMDR2--Timer Mode Register 2 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FFF1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 TPU2 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- Legend: *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.3.00 Mar. 26, 2007 Page 725 of 772 REJ09B0355-0300 Appendix B Register Field TIOR2--Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W H'FFF2 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU2 TGR2A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2A is input capture register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Legend: *: Don't care TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Legend: *: Don't care Rev.3.00 Mar. 26, 2007 Page 726 of 772 REJ09B0355-0300 Appendix B Register Field TIER2--Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- H'FFF4 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU2 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.3.00 Mar. 26, 2007 Page 727 of 772 REJ09B0355-0300 Appendix B Register Field TSR2--Timer Status Register 2 Bit : 7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 4 TCFV 0 3 -- 0 -- 2 -- 0 -- H'FFF5 1 TGFB 0 0 TGFA 0 TPU2 Initial value : Read/Write : R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 TGRA Input Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0. * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB Capture/Output Compare Flag 0 [Clearing conditions] * When DTC*2 is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0. * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Notes: 1. Can only be written with 0 for flag clearing. 2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. Rev.3.00 Mar. 26, 2007 Page 728 of 772 REJ09B0355-0300 Appendix B Register Field TCNT2--Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFF6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFF8 H'FFFA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 TPU2 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.3.00 Mar. 26, 2007 Page 729 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Reset Internal data bus Internal address bus R Q D P1nDDR C WDDR1 Reset Modes 1, 2, 3, 7 P1n Modes 4, 5, 6 R Q D P1nDR C WDR1 TPU module Output compare output/PWM output enable Output compare output/PWM output RDR1 RPOR1 Input capture input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 0 or 1 Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev.3.00 Mar. 26, 2007 Page 730 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset Internal data bus Internal address bus R Q D P1nDDR C WDDR1 Reset Modes 1, 2, 3, 7 P1n Modes 4, 5, 6 R Q D P1nDR C WDR1 TPU module Output compare output/PWM output enable Output compare output/PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 2 or 3 Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13) Rev.3.00 Mar. 26, 2007 Page 731 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 P1n RPOR1 Input capture input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 4 or 6 Figure C.1 (c) Port 1 Block Diagram (Pins P14 and P16) Rev.3.00 Mar. 26, 2007 Page 732 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 Note: n = 5 or 7 Figure C.1 (d) Port 1 Block Diagram (Pins P15 and P17) Rev.3.00 Mar. 26, 2007 Page 733 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams C.2 Port 2 Block Diagram Reset R Q D P2nDDR C WDDR2 Reset P2n R Q D P2nDR C WDR2 RDR2 RPOR2 Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Note: n = 0 or 1 Figure C.2 (a) Port 2 Block Diagram (Pins P20 and P21) Rev.3.00 Mar. 26, 2007 Page 734 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset P2n R Q D P2nDR C WDR2 RDR2 RPOR2 8-bit timer module Counter external reset input Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Note: n = 2 or 4 Figure C.2 (b) Port 2 Block Diagram (Pins P22 and P24) Rev.3.00 Mar. 26, 2007 Page 735 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset P2n R Q D P2nDR C WDR2 RDR2 RPOR2 Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Note: n = 3 or 5 Figure C.2 (c) Port 2 Block Diagram (Pins P23 and P25) Rev.3.00 Mar. 26, 2007 Page 736 of 772 REJ09B0355-0300 Internal data bus 8-bit timer module Counter external clock input Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 8-bit timer Compare-match output enable Compare-match output RDR2 P2n RPOR2 Legend: WDDR2 WDR2 RDR2 RPOR2 : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Note: n = 6 or 7 Figure C.2 (d) Port 2 Block Diagram (Pins P26 and P27) Rev.3.00 Mar. 26, 2007 Page 737 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams C.3 Port 3 Block Diagram Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 P3n RPOR3 Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR Notes: n = 0 or 1 1. Output enable signal 2. Open drain control signal Figure C.3 (a) Port 3 Block Diagram (Pins P30 and P31) Rev.3.00 Mar. 26, 2007 Page 738 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Internal data bus Serial receive data Legend: WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR Notes: n = 2 or 3 1. Output enable signal 2. Open drain control signal Figure C.3 (b) Port 3 Block Diagram (Pins P32 and P33) Rev.3.00 Mar. 26, 2007 Page 739 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C WDDR3 *2 Reset R Q D P3nDR C WDR3 *3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 P3n *1 RPOR3 Legend: WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR Notes: n = 4 or 5 1. Priority order: Serial clock input > serial clock output > DR output 2. Output enable signal 3. Open drain control signal Figure C.3 (c) Port 3 Block Diagram (Pins P34 and P35) Rev.3.00 Mar. 26, 2007 Page 740 of 772 REJ09B0355-0300 Internal data bus Serial clock input Interrupt controller IRQ interrupt input Appendix C I/O Port Block Diagrams C.4 Port 4 Block Diagram Internal data bus A/D converter module Analog input Legend: RPOR4 : Read port 4 Note: n = 0 to 3 RPOR4 P4n Figure C.4 Port 4 Block Diagram (Pins P40 to P43) Rev.3.00 Mar. 26, 2007 Page 741 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams C.5 Port 5 Block Diagram Reset R Q D P50DDR C WDDR0 Reset R Q D P50DR C WDR5 SCI module Serial transmit data output enable Serial transmit data RDR5 P50 RPOR5 Legend: WDDR5 WDR5 RDR5 RPOR5 : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5 Figure C.5 (a) Port 5 Block Diagram (Pin P50) Rev.3.00 Mar. 26, 2007 Page 742 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P51DDR C WDDR5 Reset P51 R Q D P51DR C WDR5 RDR5 RPOR5 Legend: WDDR5 : Write to P5DDR WDR5 : Write to P5DR RDR5 : Read P5DR RPOR5 : Read port 5 Figure C.5 (b) Port 5 Block Diagram (Pin P51) Rev.3.00 Mar. 26, 2007 Page 743 of 772 REJ09B0355-0300 Internal data bus SCI module Serial receive data enable Serial receive data Appendix C I/O Port Block Diagrams Reset R Q D P52DDR C WDDR5 Reset R Q D P52DR C WDR5 P52 * RDR5 RPOR5 Legend: WDDR5 WDR5 RDR5 RPOR5 : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5 Note: * Priority order: Serial clock input > serial clock output > DR output Figure C.5 (c) Port 5 Block Diagram (Pin P52) Rev.3.00 Mar. 26, 2007 Page 744 of 772 REJ09B0355-0300 Internal data bus SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input Appendix C I/O Port Block Diagrams Reset R Q D P53DDR C WDDR5 Reset P53 R Q D P53DR C WDR5 RDR5 RPOR5 Legend: WDDR5 WDR5 RDR5 RPOR5 : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5 Figure C.5 (d) Port 5 Block Diagram (Pin P53) Rev.3.00 Mar. 26, 2007 Page 745 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams C.6 Port A Block Diagram Reset R Q D PAnPCR C WPCRA RPCRA Internal data bus Modes 4, 5*3 Reset S R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA PAn Modes 1, 2, 3, 7 Modes 4, 5, 6 RDRA RPORA Legend: WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR Notes: n = 0 to 3 1. Output enable signal 2. Open drain control signal 3. Set priority Figure C.6 Port A Block Diagram (Pins PA0 to PA3) Rev.3.00 Mar. 26, 2007 Page 746 of 772 REJ09B0355-0300 Internal address bus Appendix C I/O Port Block Diagrams C.7 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB Modes 1, 4, 5* Reset S R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB PBn Modes 3, 7 Modes 1, 2, 4, 5, 6 RDRB RPORB Legend: WDDRB WDRB WPCRB RDRB RPORB RPCRB : Write to PBDDR : Write to PBDR : Write to PBPCR : Read PBDR : Read port B : Read PBPCR Notes: n = 0 to 7 * Set priority Figure C.7 Port B Block Diagram (Pins PB0 to PB7) Rev.3.00 Mar. 26, 2007 Page 747 of 772 REJ09B0355-0300 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.8 Port C Block Diagram Reset R Q D PCnPCR C WPCRC RPCRC Modes 1, 4, 5* Reset S R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Modes 3, 7 Modes 1, 2, 4, 5, 6 RDRC RPORC Legend: WDDRC : Write to PCDDR WDRC : Write to PCDR WPCRC : Write to PCPCR RDRC : Read PCDR RPORC : Read port C RPCRC : Read PCPCR Notes: n = 0 to 7 * Set priority Figure C.8 Port C Block Diagram (Pins PC0 to PC7) Rev.3.00 Mar. 26, 2007 Page 748 of 772 REJ09B0355-0300 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.9 Port D Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PDnPCR C WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Modes 3, 7 Modes 1, 2, 4, 5, 6 External address upper write External address lower write RDRD RPORD Legend: WDDRD : Write to PDDDR WDRD : Write to PDDR WPCRD : Write to PDPCR RDRD : Read PDDR RPORD : Read port D RPCRD : Read PDPCR Note: n = 0 to 7 External address upper read External address lower read Figure C.9 Port D Block Diagram (Pins PD0 to PD7) Rev.3.00 Mar. 26, 2007 Page 749 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams C.10 Port E Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn Modes 3, 7 Modes 1, 2, 4, 5, 6 RDRE RPORE Legend: WDDRE WDRE WPCRE RDRE RPORE RPCRE : Write to PEDDR : Write to PEDR : Write to PEPCR : Read PEDR : Read port E : Read PEPCR External address lower read Note: n = 0 to 7 Figure C.10 Port E Block Diagram (Pins PE0 to PE7) Rev.3.00 Mar. 26, 2007 Page 750 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams C.11 Port F Block Diagram Internal data bus Bus controller BRLE bit Bus request input Interrupt controller IRQ interrupt input Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Reset R Q D PF0DDR C Modes 1, 2, 4, 5, 6 WDDRF Reset PF0 R Q D PF0DR C WDRF RDRF RPORF Figure C.11 (a) Port F Block Diagram (Pin PF0) Rev.3.00 Mar. 26, 2007 Page 751 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Modes 1, 2, 4, 5, 6 PF1 RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.11 (b) Port F Block Diagram (Pin PF1) Rev.3.00 Mar. 26, 2007 Page 752 of 772 REJ09B0355-0300 Internal data bus Bus controller BRLE bit Bus request acknowledge output Interrupt controller IRQ interrupt input Appendix C I/O Port Block Diagrams Reset R Q D PF2DDR C WDDRF Reset Modes 1, 2, 4, 5, 6 PF2 R Q D PF2DR C WDRF Modes 1, 2, 4, 5, 6 Internal data bus Bus controller Wait enable Bus request output enable Bus request output RDRF RPORF Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Wait input Interrupt controller IRQ interrupt input Figure C.11 (c) Port F Block Diagram (Pin PF2) Rev.3.00 Mar. 26, 2007 Page 753 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D PF3DDR C WDDRF Modes 3, 7 PF3 Modes 1, 2, 4, 5, 6 Reset R Q D PF3DR C WDRF Modes 1, 2, 4, 5, 6 Internal data bus Bus controller LWR output Interrupt controller IRQ interrupt input RDRF RPORF Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Figure C.11 (d) Port F Block Diagram (Pin PF3) Rev.3.00 Mar. 26, 2007 Page 754 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D PF4DDR C WDDRF Modes 3, 7 PF4 Modes 1, 2, 4, 5, 6 Reset R Q D PF4DR C WDRF Modes 1, 2, 4, 5, 6 Internal data bus Bus controller HWR output RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.11 (e) Port F Block Diagram (Pin PF4) Rev.3.00 Mar. 26, 2007 Page 755 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D PF5DDR C WDDRF Modes 3, 7 PF5 Modes 1, 2, 4, 5, 6 Reset R Q D PF5DR C WDRF Modes 1, 2, 4, 5, 6 RDRF RPORF Legend: WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Figure C.11 (f) Port F Block Diagram (Pin PF5) Rev.3.00 Mar. 26, 2007 Page 756 of 772 REJ09B0355-0300 Internal data bus Bus controller RD output Appendix C I/O Port Block Diagrams Reset R Q D PF6DDR C WDDRF Modes 3, 7 PF6 Modes 1, 2, 4, 5, 6 Reset R Q D PF6DR C WDRF Modes 1, 2, 4, 5, 6 RDRF RPORF Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Figure C.11 (g) Port F Block Diagram (Pin PF6) Rev.3.00 Mar. 26, 2007 Page 757 of 772 REJ09B0355-0300 Internal data bus Bus controller AS output Appendix C I/O Port Block Diagrams Modes 1, 2, 4, 5, 6* Reset S R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF RDRF RPORF Legend: WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Note: * Set priority Figure C.11 (h) Port F Block Diagram (Pin PF7) Rev.3.00 Mar. 26, 2007 Page 758 of 772 REJ09B0355-0300 Internal data bus Appendix C I/O Port Block Diagrams C.12 Port G Block Diagram Reset R Q D PG0DDR C WDDRG Reset PG0 R Q D PG0DR C WDRG RDRG RPORG Internal data bus A/D converter A/D converter external trigger input Interrupt controller IRQ interrupt input Legend: WDDRG : Write to PGDDR WDRG : Write to PGDR RDRG : Read PGDR RPORG : Read port G Figure C.12 (a) Port G Block Diagram (Pin PG0) Rev.3.00 Mar. 26, 2007 Page 759 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D PG1DDR C WDDRG Modes 1, 2, 3, 7 PG1 Modes 4, 5, 6 Reset R Q D PG1DR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Interrupt controller IRQ interrupt input Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.12 (b) Port G Block Diagram (Pin PG1) Rev.3.00 Mar. 26, 2007 Page 760 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Reset R Q D PGnDDR C WDDRG Modes 1, 2, 3, 7 PGn Modes 4, 5, 6 Reset R Q D PGnDR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Note: n = 2 or 3 Figure C.12 (c) Port G Block Diagram (Pins PG2 and PG3) Rev.3.00 Mar. 26, 2007 Page 761 of 772 REJ09B0355-0300 Appendix C I/O Port Block Diagrams Modes 1, 4, 5 Reset Modes 2, 3, 6, 7 WDDRG Reset Modes 3, 7 PG4 Modes 1, 2, 4, 5, 6 R Q D PG4DR C WDRG RDRG RPORG Legend: WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C.12 (d) Port G Block Diagram (Pin PG4) Rev.3.00 Mar. 26, 2007 Page 762 of 772 REJ09B0355-0300 Internal data bus S R Q D PG4DDR C Bus controller Chip select Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode I/O Port States in Each Processing State MCU Operating Mode Hardware Software Standby Standby Mode Mode T kept Bus Release State kept Program Execution State Sleep Mode I/O port Table D.1 Port Name Pin Name Power-On Manual Reset Reset T kept P17/TIOCB2/ 1 to 7 TCLKD P16/TIOCA2 P15/TIOCB1/ TCLKC P14/TIOCA1 P13/TIOCD0/ 1 to 3, 7 TCLKB/A23 4 to 6 P12/TIOCC0/ TCLKA/A22 P11/TIOCB0/ A21 P10/TIOCA0/ A20 Port 2 Port 3 Port 4 Port 5 Port A 1 to 7 1 to 7 1 to 7 1 to 7 1 to 3, 7 4, 5 T T kept kept T T kept kept I/O port [DDR = 0] Input port [DDR = 1] Address output [DDR * OPE = 0] T T [DDR * OPE = 1] kept T T T T T L kept kept T kept kept kept T T T T T T kept kept T kept kept [OPE = 0] T [OPE = 1] kept kept kept T kept kept T I/O port I/O port Input port I/O port I/O port Address output 6 T kept T [DDR * OPE = 0] T T [DDR * OPE = 1] kept [DDR = 0] Input port [DDR = 1] Address output Rev.3.00 Mar. 26, 2007 Page 763 of 772 REJ09B0355-0300 Appendix D Pin States Program Execution State Sleep Mode Address output Port Name Pin Name Port B MCU Operating Mode 1, 4, 5 Power-On Manual Reset Reset L kept Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] kept Bus Release State T 2, 6 T kept T [DDR * OPE = 0] T T [DDR * OPE = 1] kept [DDR = 0} Input port [DDR = 1] Address output 3, 7 Port C 1, 4, 5 T L kept kept T T kept [OPE = 0] T [OPE = 1] kept kept T I/O port Address output 2, 6 T kept T [DDR * OPE = 0] T T [DDR * OPE = 1] kept [DDR = 0] Input port [DDR = 1] Address output 3, 7 Port D 1, 2, 4 to 6 3, 7 Port E 1, 2, 8-bit 4 to 6 bus T T T T kept T kept kept T kept T T T T T T kept T kept kept T kept kept T kept kept T kept I/O port Data bus I/O port I/O port Data bus I/O port 16-bit T bus 3, 7 T Rev.3.00 Mar. 26, 2007 Page 764 of 772 REJ09B0355-0300 Appendix D Pin States Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output AS, RD, HWR, LWR Port Name Pin Name PF7/ MCU Operating Mode 1, 2, 4 to 6 Power-On Manual Reset Reset Clock output Hardware Software Standby Standby Mode Mode [DDR = 0] Input port [DDR = 1] H T [DDR = 0] Input port [DDR = 1] H Bus Release State [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output T [DDR = 0] T Input port [DDR = 1] Clock output 3, 7 T kept PF6/AS PF5/RD PF4/HWR PF3/LWR/ IRQ3 PF2/WAIT/ BREQO/ IRQ2 1, 2, 4 to 6 H H T [OPE= 0] T [OPE = 1] H 3, 7 1, 2, 4 to 6 T T kept kept T T kept [BREQOE + WAITE = 0] kept [BREQOE = 1, WAITE = 0] kept [BREQOE = 0, WAITE = 1] T kept [BREQOE + WAITE = 0] kept I/O port [BREQOE + WAITE = 0] I/O port [BREQOE = 1, [BREQOE = 1, WAITE = 0] WAITE = 0] BREQO BREQO [BREQOE = 0, [BREQOE= 0, WAITE = 1] WAITE = 1] WAIT T kept L I/O port [BRLE = 0] I/O port [BRLE = 1] BACK kept T I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ kept I/O port 3, 7 PF1/BACK/ IRQ1 1, 2, 4 to 6 T T kept kept T T kept [BRLE = 0] kept [BRLE = 1] H 3, 7 PF0/BREQ/ IRQ0 1, 2, 4 to 6 T T kept kept T T kept [BRLE = 0] kept [BRLE = 1] T 3, 7 T kept T kept Rev.3.00 Mar. 26, 2007 Page 765 of 772 REJ09B0355-0300 Appendix D Pin States Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] CS0 (in sleep mode, H) kept kept I/O port I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3 kept I/O port Port Name Pin Name PG4/CS0 MCU Operating Mode 1, 4, 5 2, 6 Power-On Manual Reset Reset H T kept Hardware Software Standby Standby Mode Mode T Bus Release State [DDR * OPE = 0] T T [DDR * OPE = 1] H 3, 7 PG3/CS1 PG2/CS2 PG1/CS3/ IRQ0 1 to 3, 7 4 to 6 T T T kept kept kept T T T kept kept [DDR * OPE = 0] T T [DDR * OPE = 1] H PG0/ADTRG/ 1 to 7 IRQ6 T kept T kept Legend: H: L: T: kept: DDR: OPE: WAITE: BRLE: BREQOE: High level Low level High impedance Input port becomes high-impedance, output port retains state Data direction register Output port enable Wait input enable Bus release enable BREQO pin enable Rev.3.00 Mar. 26, 2007 Page 766 of 772 REJ09B0355-0300 Appendix E Pin States at Power-On Appendix E Pin States at Power-On Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. After reset release, power-on reset exception handling is started. Note: * "Settle" refers to the pin states in a power-on reset in each MCU operating mode. E.1 When Pins Settle from an Indeterminate State at Power-On When the NMI pin level changes from low to high after powering on, the chip goes to the poweron reset state after a high level is detected at the NMI pin. While the chip detects a low level at the NMI pin, the manual reset state is established. The pin states are indeterminate during this interval. (Ports may output an internally determined value after powering on.) The NMI setup time (tNMIS) is necessary for the chip to detect a high level at the NMI pin. VCC tOSC1 STBY Manual reset Power-on reset NMI RES NMI = Low NMI = High RES = Low Figure E.1 When Pins Settle from an Indeterminate State at Power-On Rev.3.00 Mar. 26, 2007 Page 767 of 772 REJ09B0355-0300 Appendix E Pin States at Power-On E.2 When Pins Settle from the High-Impedance State at Power-On When the STBY pin level changes from low to high after powering on, the chip goes to the poweron reset state after a high level is detected at the STBY pin. While the chip detects a low level at the STBY pin, it is in the hardware standby mode. During this interval, the pins are in the highimpedance state. After detecting a high level at the STBY pin, the chip starts oscillation. VCC tOSC1 STBY Hardware standby mode Power-on reset NMI T1 RES Confirm t1min and tNMIS. NMI = High RES = Low Figure E.2 When Pins Settle from the High-Impedance State at Power-On Rev.3.00 Mar. 26, 2007 Page 768 of 772 REJ09B0355-0300 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown figure F.1. RES must remain low until STBY goes low (delay from STBY fall to RES rise: minimum 0 ns). STBY t1 10 tcyc RES t2 0 ns Figure F.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high, and execute a power-on reset. STBY t 100 ns RES tOSC tNMIRH NMI Figure F.2 Timing of Recovery from Hardware Standby Mode Rev.3.00 Mar. 26, 2007 Page 769 of 772 REJ09B0355-0300 Appendix G Product Code Lineup Appendix G Product Code Lineup Product Type H8S/2246 Mask ROM version Part No. HD6432246 Mark Code HD6432246FA HD6432246TE ZTAT version HD6472246 HD6472246FA HD6472246TE H8S/2245 Mask ROM version HD6432245 HD6432245FA HD6432245TE H8S/2244 HD6432244 HD6432244FA HD6432244TE H8S/2243 HD6432243 HD6432243FA HD6432243TE H8S/2242 HD6432242 HD6432242FA HD6432242TE H8S/2241 HD6432241R HD6432241RFA HD6432241RTE H8S/2240 ROMless version HD6412240 HD6412240FA HD6412240TE Package (Package Code) 100 pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) Rev.3.00 Mar. 26, 2007 Page 770 of 772 REJ09B0355-0300 Appendix H Package Dimensions Appendix H Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 50 bp b1 c1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 1 ZD 25 F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0 Min A A2 Figure H.1 FP-100B Package Dimensions Rev.3.00 Mar. 26, 2007 Page 771 of 772 REJ09B0355-0300 c Appendix H Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 51 75 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 A2 1 ZD Index mark 25 A F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.00 1.00 0.4 0.5 0.6 1.0 Min Figure H.2 TFP-100B Package Dimensions Rev.3.00 Mar. 26, 2007 Page 772 of 772 REJ09B0355-0300 c Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2245 Group Publication Date: 1st Edition, December 1996 Rev.3.00, March 26, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8S/2245 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
Price & Availability of HD6432241RFA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |